Dear all,
I'm currently working on a self-checking automatic testbench in Verilog-AMS for IP modules. I have Ken's book (designer's guide to Verilog-AMS), but i still have a few questions:
Is it possible to create a pointer to an input or output of a model, in combination with a task or function ? For example if i have this code(not checked at all!!):
Code:module testblock(input1, input2, output1, output2);
input input1, input2;
ouput output1, output2;
electrical input1, input2;
logic output1, output2;
.....
....
(some more code)
begin
task_check_input(&input1);
end
task_check_input;
input choice_input;
real *choice_input;
real voltage;
begin
voltage <= V(choice_input,gnd);
......
end
endtask
Ofcource it is possible to constantly monitor a analog value within the analog statements in verilog-ams. I'm just wondering if it is possible to use pointers within Verilog-AMS. I can imagine that it is not posible although..
Second question i have, is about the verification of a behaviour model v.s. a transistormodel. Does anybody knows how to verify the two models with 1 (verilog-ams) testbench at the same time. At this point i am simulation the behaviour model and the transistor model seperate, and then compare the output of both models but i would like to do this in 1 check. Does someone has a tip
Kind regards,
IJnte