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HVMOS gate delay verification (Read 3071 times)

hoak New Member Offline Posts: 2	HVMOS gate delay verification Feb 16^th, 2009, 10:43pm Dear all, As we know, we can design R.O. to verify the gate delay for LV MOS model. I want to know how to verify it for HVMOS model. Could you please tell me the solutions about this? Thanks. BR, Hoak
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Geoffrey_Coram

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Massachusetts, USA

Re: HVMOS gate delay verification
Reply #1 - Feb 24^th, 2009, 6:21am

R.O. = ring oscillator? (best not to use abbreviations in your first post)

Do you have HVMOS gates? I guess the point with a ring oscillator is that there isn't an external source with an artificial transition -- eg, too fast a rise time on your pulse or PWL source. So, for HVMOS, you should probably put in "enough" gates that the rise and fall times are determined by the HVMOS devices rather than the input source.

If at first you do succeed, STOP, raise your standards, and stop wasting your time.

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hoak New Member Offline Posts: 2	Re: HVMOS gate delay verification Reply #2 - Feb 25^th, 2009, 12:34am ,yes. We can use oscillograph to measure it. But for HV MOS or power MOS, is there any method to evaluate this gate delay? BR, hoak
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