Hi,
My experience was(and I didn't have any previous experience with modifying foundry models) that its about one or two hours for each model that you want to modify, the most difficult part that I found was translating mismatch specs to BSIM parameters(I didn't have a deep understanding of BSIM models at that time) since if foundry provides mismatch data for IDS variation you should translate to a primary BSIM model that doesn't affect other parameters of the model. I more or less followed that reference:

Papathanasiou, K., A designer’s approach to device mismatch: Theory,
modeling,simulation techniques, scripting, applications and examples. Analog Integrated Circuits Signal Processing 2006

and the BSIM3 users manual. One change (my error respect foundry reports when I did simulations with current mirrors was below 1%) respect to that paper is that it uses dependent sources to model mismatch, to avoid increasing netlisting a lot I prefered to use a "average" mismatch model(that is data fitting with Matlab,averaging and obtain the standard equation K/sqrt(WL)+C using a minimum square error fitting) and embed directly into BSIM models parameters ( that is the standard foundry approach I think based on what I see in several design kits).

In the end I ended up with modifications like the following in BSIM models:
vth0=original_term+  dvthp*(K/sqrt(nf*W*L)+cte)
u0=original_term + du0*(Ku0/sqrt(nf*W*L)+cte)

Also you should modify the "PDK structure" to put an specific section like the TT,SS,FF that I called MC so you could put and statistics and mismatch section.

Hope it helps,

PS:sorry for the long post, if you need further information don't hesitate to ask.

Hi if we open modelfile we can see a function like aguass(0,1,1)
[1]What this function will do
[2]What is the significance of each parameter in that function
[3]Montecarlo considers wafer to wafer variation or die to die variation

[1]In PVT all the transistors in the circuit will be at same corner(like TT or FF or SS or SF or FS)
[2]Suppose if all the transistors are not at the same corner .one transistor is at one corner and the second transistor is at other corner.Then what we called it as it is a mismatch model or monte carlo model

Hi what is meant by absolute variation and relative variation

http://books.google.com/books?id=3cAuzDM-N6wC&printsec=frontcover
gives a good explanation of the inter and intra dies variations.

Does anybody here know how to run Monte Carlo sims - local variations in Hspice by specifying the global point? I have done the global variation on a 6t SRAM and would want to do a local variation now.

The term "local" is probably being used to indicate device to device variation (i.e. mismatch), whereas "global" is die to die variation (i.e. process variation).

Monte Carlo allows you to generate a set of models based on statistical parameters, usually representing the process spread and/or mismatch spread of the particular process. For process ("global") variation, for each statistical variable you generate a new value per point in the run; for mismatch ("local") variation, you generate a new value per device in the design. Consequently you are generating a set of points across the process/mismatch distribution (assuming the modeling is done well).

Corners just pick extreme values of the same variables, and typically you get all the extremes at once - these are statistically very unlikely to occur. You can also end up with false corners - corners that will never in practice occur, because you are taking devices in opposite directions, when in fact some of the parameters are correlated. You also can end up missing large regions of the process space.

Typically corners leads to over-design, because you make your design bomb-proof in corners that are never likely to happen. Occasionally you can be unlucky and end up with designs that fail because you're missing out the central regions where devices normally will be. The advantage is that corner simulation is fast, because you don't have many points to simulate.

In some simulators (e.g. spectre) you have the option with Monte Carlo of performing "Latin Hypercube Sampling" (see Wikipedia for an explanation) which reduces the typical number of points needed to get good coverage of the distribution. Some foundries have used a Latin Hypercube sampling approach to generate "corners" which are spread over the process - for example, one I know has 25 "corners" (I put the word in quotation marks, since they're not in the corners of the process) to give a better representation of the process.

Normally you don't statistically vary voltage or temperature, because voltage and temperature are usually hard specification limits - your design has to work at low and high voltage extremes, and same for temperature. So you need to simulate at the extremes for certain.

So to be thorough, you'd use corners for the "VT" part, and monte carlo at each corner for the process/mismatch variation.

Best Regards,

Andrew.

In IC5141, you can use Tools->Monte Carlo (from ADE) and there you can set the variation to be "Process", "Mismatch" or  "Process + Mismatch" (I forget exactly what it says). As I said before "Process" is the same as "Global", and "Mismatch" is the same as "Local".

In IC613 in ADE XL, you would choose Monte Carlo Sampling run mode, and then in the Run options you can choose "Process", "Mismatch" or "All".

Regards,

Andrew.