i'm trying to simulate the effects of changing vdd and vth on digital circuits.  people do this  to trade off active power, static power, and speed.

for a given technology, architecture, target frequency, and input set, there's unique solution to vdd and vth that minimizes power avg power.

all of the papers i've seen that propose solutions to this problem start w/ simple equations for on-current, off-current, and delay.  its probably the only way to get an analytical solution.

what i don't see is people verifying their results w/ simulation to see how good their approximations were.

simulating the effects of changing vdd is trivial, its outside the model.  however, how should one go about changing the threshold?

there are many factors that go into the threshold derivation in these models. and to my knowledge, there's no physical way to change the threshold w/o changing some other aspect of the transistor. some major examples being: mobility in the case of channel implants, gate capacitance in the case of oxide thickness, etc.

and that's fine, its just these second-order effects i'm trying to simulate.

so my question is-- sorry i took so long to get to it-- what parameters do i need to change (bsim3, 4, ekv, whatever) to accurately reflect threshold adjustment through channel ion implantation, oxide thickness  scaling, etc?

just trying to avoid making unrealistic models here.

thanks