I'm now using ADSsim, Ptolemy and NCSim for this purpose. I don't use Cadence AMSD.

Here I use Verilog-AMS of ADSsim to do cosimulation with NCSim.

And I use many models which are built by FDD and system model library even in Cadence Composer schematic.

Agilent recommended users to use WTB in RFDE if they want to use Ptolemy models in Cadence Design Environment.

But I don't use WTB. Instead I use dynamic link if I have to use Ptolemy models.

Although I also have MATLAB/Simulink, I don't use it for cosimulation with continous time domain simulator.

Since I have incisive link of Simulink, I do cosimulation between Simulink and NCSim.

**currant wrote on Mar 28**^{th}, 2009, 5:15am:I am thinking about ADS with Dynamic Link, but don't know how system simulation (Ptolemy) will work with circuits from cadence.

Ptolemy models can be available as WTB in Cadence Design Environment.

You can also use them by Dynamic Link where master analysis controler is Ptolemy and slave analysis is ADSsim.

As far as you use Verilog-AMS models, hidden states problem exist also in ADS.

But ADS have FDD modeling ability. If you write own models by this FDD, you can use them even in envelope analysis.

And big advantages of ADS is that ADS has rich system model library which are available even in envelope analysis.

Since they are available as netlist, it is easy to use them in Cadence Composer schematic.

But dynamic link and RFDE are terminated in ADS2009.

http://www.designers-guide.org/Forum/YaBB.pl?num=1237378629/1#1**currant wrote on Mar 28**^{th}, 2009, 5:15am:But I worry about system simulation, because spectreRF suffer from hidden states, that are being in FIR filters for example.

You are right. This problem is also true for Verilog-AMS.

See

http://www.designers-guide.org/Forum/YaBB.pl?num=1234618137**currant wrote on Mar 28**^{th}, 2009, 5:15am:And main problem - full top-down design, preferable, without problem connections betwen tools.

Especialy, I guess problems in hierarchical design, when I will need verify circuits of blocks in system bench.

Here you should consider following isuues.

- Fast Transient Analysis without loss of accuracy

- Fast Envelope Analysis

- Cosimulation with Logic Simulator such as Cadence NCSim using Verilog-AMS or Verilog-D

- Cosimulation with system simulator such as Agilent Ptolmey or MathWorks Simulink

Instead of ADSsim, I will use Agilent GoldenGate with Verilog-AMS to do cosimulation with Cadence NCSim.

Here Ptolemy models can be imported into GoldenGate. But they are limited to sink and source models now.

Envelope analysis of GoldenGate is very fast.

To my regret, FDD custom models and system model library are not avaliable in current GoldenGate.

We can't use Verilog-AMS models which have hidden states if we will use envelope analysis.

However for transient analysis, we can use Verilog-AMS models which have hidden states.

So I want to introduce BDA's FastSpice which is possible to do cosimulation with Cadence NCSim.

http://www.designers-guide.org/Forum/YaBB.pl?num=1183646486/11#11So simulators in my environments are :

- Agilent ADSsim (to be terminated)

- Agilent Ptolemy

- Agilent GoldenGate (to be introduced instead of ADSsim)

- Cadence NCSim

- BDA's FastSpice (want to introduce)

If you prefer Cadence Tools, use Cadence AMSD.

Here Agilent Ptolemy models can be imported into Cadence AMSD.

And you can do cosimulation with MathWorks Simulink.

- Cadence AMSD(MMSIM and NCSim)

- MathWorks Simulink

- Agilent Ptolemy