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Complex Analog/RF/DSP IC design tool/flow (Read 28433 times)
currant
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Complex Analog/RF/DSP IC design tool/flow
Mar 28th, 2009, 5:15am
 
Hi,
I've a task of design complex ICs, which will use in communication systems like TETRA, and consists of some RF part, bandpass SD-ADC and some digital filters.

And main problem - full top-down design, preferable, without problem connections betwen tools. Especialy, I guess problems in hierarchical design, when I will need verify circuits of blocks in system bench.

Could anybody help me about preferable set of tools, one of which is Cadence IC?

Cadence very good design environment while one works with lumped components ( as is on my design).
But I worry about system simulation, because spectreRF suffer from hidden states, that are being in FIR filters for example.
I am thinking about ADS with Dynamic Link, but don't know how system simulation (Ptolemy) will work with circuits from cadence.
What kind of problem can I meet in this couple of tools?
Does anybody create complex RFIC by this way or may be one another flow?

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pancho_hideboo
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Re: Complex Analog/RF/DSP IC design tool/flow
Reply #1 - Mar 28th, 2009, 5:27am
 
I'm now using ADSsim, Ptolemy and NCSim for this purpose. I don't use Cadence AMSD.
Here I use Verilog-AMS of ADSsim to do cosimulation with NCSim.
And I use many models which are built by FDD and system model library even in Cadence Composer schematic.
Agilent recommended users to use WTB in RFDE if they want to use Ptolemy models in Cadence Design Environment.
But I don't use WTB. Instead I use dynamic link if I have to use Ptolemy models.
Although I also have MATLAB/Simulink, I don't use it for cosimulation with continous time domain simulator.
Since I have incisive link of Simulink, I do cosimulation between Simulink and NCSim.

currant wrote on Mar 28th, 2009, 5:15am:
I am thinking about ADS with Dynamic Link, but don't know how system simulation (Ptolemy) will work with circuits from cadence.

Ptolemy models can be available as WTB in Cadence Design Environment.
You can also use them by Dynamic Link where master analysis controler is Ptolemy and slave analysis is ADSsim.
As far as you use Verilog-AMS models, hidden states problem exist also in ADS.
But ADS have FDD modeling ability. If you write own models by this FDD, you can use them even in envelope analysis.
And big advantages of ADS is that ADS has rich system model library which are available even in envelope analysis.
Since they are available as netlist, it is easy to use them in Cadence Composer schematic.
But dynamic link and RFDE are terminated in ADS2009.
http://www.designers-guide.org/Forum/YaBB.pl?num=1237378629/1#1

currant wrote on Mar 28th, 2009, 5:15am:
But I worry about system simulation, because spectreRF suffer from hidden states, that are being in FIR filters for example.
You are right. This problem is also true for Verilog-AMS.
See http://www.designers-guide.org/Forum/YaBB.pl?num=1234618137

currant wrote on Mar 28th, 2009, 5:15am:
And main problem - full top-down design, preferable, without problem connections betwen tools.
Especialy, I guess problems in hierarchical design, when I will need verify circuits of blocks in system bench.

Here you should consider following isuues.
 - Fast Transient Analysis without loss of accuracy
 - Fast Envelope Analysis
 - Cosimulation with Logic Simulator such as Cadence NCSim using Verilog-AMS or Verilog-D
 - Cosimulation with system simulator such as Agilent Ptolmey or MathWorks Simulink

Instead of ADSsim, I will use Agilent GoldenGate with Verilog-AMS to do cosimulation with Cadence NCSim.
Here Ptolemy models can be imported into GoldenGate. But they are limited to sink and source models now.
Envelope analysis of GoldenGate is very fast.
To my regret, FDD custom models and system model library are not avaliable in current GoldenGate.
We can't use Verilog-AMS models which have hidden states if we will use envelope analysis.
However for transient analysis, we can use Verilog-AMS models which have hidden states.
So I want to introduce BDA's FastSpice which is possible to do cosimulation with Cadence NCSim.
http://www.designers-guide.org/Forum/YaBB.pl?num=1183646486/11#11
So simulators in my environments are :
 - Agilent ADSsim (to be terminated)
 - Agilent Ptolemy
 - Agilent GoldenGate (to be introduced instead of ADSsim)
 - Cadence NCSim
 - BDA's FastSpice (want to introduce)

If you prefer Cadence Tools, use Cadence AMSD.
Here Agilent Ptolemy models can be imported into Cadence AMSD.
And you can do cosimulation with MathWorks Simulink.
 - Cadence AMSD(MMSIM and NCSim)
 - MathWorks Simulink
 - Agilent Ptolemy

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« Last Edit: Mar 28th, 2009, 10:02pm by pancho_hideboo »  
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Visjnoe
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Re: Complex Analog/RF/DSP IC design tool/flow
Reply #2 - Mar 28th, 2009, 6:45am
 
The tool suite from Agilent is complete, but rather expensive.

Most FastSPICE simulator can handle a combination of Verilog/VHDL/Verilog-AMS/SPICE so that is the way to go for your full-chip simulation. Most of these are however limited to transient analysis.

If you want to avoid these problems, you can simulate the analog portion using your tool of choice and write the output of the ADC to some temporary file which you take as input of your digital portion.

Regards

Peter
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pancho_hideboo
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Re: Complex Analog/RF/DSP IC design tool/flow
Reply #3 - Mar 28th, 2009, 6:53am
 
Visjnoe wrote on Mar 28th, 2009, 6:45am:
The tool suite from Agilent is complete, but rather expensive.
I think Cadence AMSD is most expensive.

Visjnoe wrote on Mar 28th, 2009, 6:45am:
Most FastSPICE simulator can handle a combination of Verilog/VHDL/Verilog-AMS/SPICE so that is the way to go for your full-chip simulation.
I also have HSIM and NanoSim of Synopsys.
But Cosimulation of Nanosim and VCS is very lacking in accuracy for RF applications.
Cosimulation of HSIM and VCS might be useful for RF applications compared to NanoSim to some extent.
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« Last Edit: Mar 28th, 2009, 9:30pm by pancho_hideboo »  
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currant
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Re: Complex Analog/RF/DSP IC design tool/flow
Reply #4 - Mar 28th, 2009, 6:56am
 
Many Thanks,  pancho_hideboo!
You are first one, who answer  this question so in detail!

 For my regret, I don't know what is FDD (maybe frequency domain)?

  There is one problem. Circuit designers works in Cadence and uses spectreRF analysis, but I have to take their circuits and try to verify in my system model, and I until now don't find teqnique to do this. And it is seems,  that  Cadence Virtuoso+Dynamik Link+Ptolemy is most seamless method to simulate analog/RF circuits in system-level model environment with minimal loss of accuracy. And unique feature of Ptolemy - uses,  at the same time, three type of analysis.

  In this moment I talk mainly about Analog/RF not digital (which I  wanted create on Verilog-A/AMS until now).

 But there are two bad news: about Dynamik Link and problems with hidden states in Ptolemy.
  
 I thought  about MATLAB, but it allows to work only on Verilog-A model level, and there is no way to simulate transistor level circuits.
 
 Is there not enough use only Ptolemy source/and sink in GG flow, so co-simulation with Ptolemy would be realized through files?
  
 Sorry for my Russian English ).
 
 

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currant
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Re: Complex Analog/RF/DSP IC design tool/flow
Reply #5 - Mar 28th, 2009, 7:32am
 
 I meant: SDF/TSDF, Tran, Envelope, as I undestand: system is simulated by DataFlow controller, but in model one may uses blocks with internal Tran or Envelope controller.

  About MATLAB. As I know, MATLAB can work with Verilog-A models, may be I wrong. s-parameters is valid mainly for RF linear blocks, but how could I simulate in MATLAB OPAMP with distortions and without creating top-level model for the circuit ? I thought, that in Ptolemy I could be, via Dynamik Link, simulate OPAMP circuits  by Tran Analys in system, that is simulated by DataFlow analys. am I wrong?
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currant
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Re: Complex Analog/RF/DSP IC design tool/flow
Reply #6 - Mar 28th, 2009, 8:00am
 
 Yes, I have no practic in simulation with Ptolemy.
 Could You breifly explain what can I  expect from co-simulation cadence analog/RF circuits with Ptolemy (or give some links for reading)?

Sorry, of course, I meant Simulink.
 
From Ptolemy datasheet:
   In ADS Ptolemy, a complex system is specified as a hierarchical composition (nested tree
structure) of simpler circuits. Each subnetwork is modeled by a domain. A subnetwork can
internally use a different domain than that of its parent. In mixing domains, the key is to
ensure that at the interface, the child subnetwork obeys the semantics of the parent
domain.
Thus, the key concept in ADS Ptolemy is to mix models of computation, implementation
languages, and design styles, rather than trying to develop one, all-encompassing
technique.
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pancho_hideboo
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Re: Complex Analog/RF/DSP IC design tool/flow
Reply #7 - Mar 28th, 2009, 8:21am
 
It seems that you can't arrive at enough level to understand "Complex Analog/RF/DSP IC design tool/flow".

currant wrote on Mar 28th, 2009, 8:00am:
 Yes, I have no practice in simulation with Ptolemy.
It also seems that you have no experience of using both Simulink and Ptolemy.

Both Simulink and Ptolemy are classified as DT(Discrete Time) or TSDF(Timed Synchronous Data Flow) Simulator.
Models of both Ptolemy and Simulink are signal flow model(not energy conservative system).
On the other hand, models of Verilog-A are energy conservative system which have flow and potential.
Of course you can use Verilog-A for signal flow modeling.

Although Ptolemy have only fixed time step solver, Simulink have both continuous and fixed time step solvers.
About performance as DT simulator, Simulink is superior than Ptolemy.
Agilent might replace Ptolemy with SystemVue.

currant wrote on Mar 28th, 2009, 8:00am:
Sorry, of course, I meant Simulink.
If you have Simulink, see RF Blockset.
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« Last Edit: Mar 28th, 2009, 9:42pm by pancho_hideboo »  

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currant
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Re: Complex Analog/RF/DSP IC design tool/flow
Reply #8 - Mar 28th, 2009, 8:33am
 
This information, absolutely that I need.

 I know about  RF blockset and work with Simulink .
 The main point in question was: How simulate transistor level circuits from cadence Virtuoso in different fom Virtuoso system simulator without translation from circuit to system set of parameters such of S param, IIP3, NF and etc.
  may be this is incorrect question.

  But now, I know set of tools, that could be use in this task and some limits of tools.


  Many thanks,  pancho_hideboo!
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pancho_hideboo
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Re: Complex Analog/RF/DSP IC design tool/flow
Reply #9 - Mar 28th, 2009, 8:42am
 
currant wrote on Mar 28th, 2009, 6:56am:
And it is seems, that Cadence Virtuoso+Dynamik Link+Ptolemy is most seamless method to simulate analog/RF circuits in system-level model environment with minimal loss of accuracy.
You can do same tasks by using Cadence AMSD with importing Ptolemy models.
Here you can also do cosimulation with Simulink. And you can also import models of SPW(CoWare SPD).
On the other hand, if you use Agilent Dynamic Link,
you can not use models of Simulink, although you can do cosimulation with m-files of MATLAB.

currant wrote on Mar 28th, 2009, 6:56am:
But there are two bad news: about Dynamik Link and problems with hidden states in Ptolemy.
You don't have to care about hidden states of Ptolemy models. This is also true for models of Simulink with Cadence AMSD.

currant wrote on Mar 28th, 2009, 7:32am:
I meant: SDF/TSDF, Tran, Envelope, as I undestand: system is simulated by DataFlow controller, but in model one may uses blocks with internal Tran or Envelope controller.
Your classification of analysis or domain is not correct.
In Mixed-signal systems, you need mixed analysis of following three domains.

  - CT(Continuous Time) ; Tran, Envelope
  - DT(Discrete Time) ; SDF/TSDF simulator such as Ptolemy, Simulink, SPW(CoWare SPD), SystemVue, etc.
  - DE(Discrete Event or Event Driven) ; NCSim, VCS, ModelSim

If you use Agilent Dynamic Link or WTB, master controller is DT.
If you use Agilent GoldenGate, master controller is CT.
If you use Cadence AMSD, master controller is DE.
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« Last Edit: Mar 28th, 2009, 10:10pm by pancho_hideboo »  
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Re: Complex Analog/RF/DSP IC design tool/flow
Reply #10 - Mar 28th, 2009, 9:19am
 
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« Last Edit: Mar 28th, 2009, 9:54pm by pancho_hideboo »  
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Re: Complex Analog/RF/DSP IC design tool/flow
Reply #11 - Mar 29th, 2009, 7:49pm
 
The whole co-simulation issue is complicated by the different timescale's required. To do transistor level simulations, you need a simulation timestep that supports the interesting signal bandwiths.

If you are looking at a 2 GHz system, you might want to simulate up to the 5th harmonic, so you'd want to set your simulation bandwidth to 10 MHz. However, this gives you a timestep requirement of 50 nSec. However, if you are trying to look at spectral mask performance in a transmitter, you'll need to transmit thousands of bits to get a good mask. If your datarate is 1 MBit/sec, you might need to have a simulation length of 1 mSec, or 20 million timesteps. Doing co-simulation is pretty complicated, and needs a fair amount of attention to set up so you get reasonable answers out.

Dave
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Re: Complex Analog/RF/DSP IC design tool/flow
Reply #12 - Mar 30th, 2009, 1:19am
 
DaveB wrote on Mar 29th, 2009, 7:49pm:
If you are looking at a 2 GHz system, you might want to simulate up to the 5th harmonic, so you'd want to set your simulation bandwidth to 10 MHz. However, this gives you a timestep requirement of 50 nSec.
Don't you have typos ? Correctly they are 10GHz and 50psec(=1/(2*10GHz)) ?
And generally your estimation is not enough.
I use time step lesser than 20psec(=1/(5*10GHz)) for 10GHz System.

DaveB wrote on Mar 29th, 2009, 7:49pm:
If your datarate is 1 MBit/sec, you might need to have a simulation length of 1 mSec, or 20 million timesteps.
Your example is a cosimulation using transient analysis.
If we use envelope analysis and both target circuit and modulation scheme are well suited to envelope analysis, time points will be largely reduced.

There is important issue in transient analysis for RF system even if we use BDA's FastSpice.
Time step of current commercial transient analysis iteself is single rate over whole circuits.
This is true for saved data.

You should save data using different time step for RF signal and IF or BB signal.
Here you need sink component to capture signal at different time step.
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« Last Edit: Mar 30th, 2009, 9:37am by pancho_hideboo »  
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currant
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Re: Complex Analog/RF/DSP IC design tool/flow
Reply #13 - Apr 14th, 2009, 1:55am
 
Hi,  pancho_hideboo.

Once again, thank You for help!

Now, I am  using evalution version of ADS2009 (Dynamic Link still exist), and I have a question.
When  I try to use DynamikLink, I find  some problems. For example ADSSim does't undestandt mos0 primitive. In spite of the fact that this is a simple model and doesn't use in real devices, I am worry.

Did You have any problem with simulation Spectre models from real PDK by ADSSim ?
 Do I need to have special models  for ADSSim if I use DynamikLink?

 And would I need special models  for ADSSim, if I don't use dynamikLink and work on level of import/export netlist?  

Thanks!


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pancho_hideboo
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Re: Complex Analog/RF/DSP IC design tool/flow
Reply #14 - Apr 14th, 2009, 3:41am
 
currant wrote on Apr 14th, 2009, 1:55am:
Did You have any problem with simulation Spectre models from real PDK by ADSSim ?
I had no problem.

currant wrote on Apr 14th, 2009, 1:55am:
Do I need to have special models  for ADSSim if I use DynamikLink?
No, you don't need any special model.

How do you include model file in ADS schematics ? Do you surely put "netlist_include" component which specify model files in Spectre Syntax ?
Show me your netlist of Dynamic Link.

currant wrote on Apr 14th, 2009, 1:55am:
And would I need special models  for ADSSim, if I don't use dynamikLink and work on level of import/export netlist?
I can't understand meaning of your qurestion.

ADSsim can understand netlists of Cadence Spectre Syntax directly.
See the followings.
http://www.designers-guide.org/Forum/YaBB.pl?num=1205223090
http://www.designers-guide.org/Forum/YaBB.pl?num=1216663909




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