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franco

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how to run pnoise simulation of oscillator + buffer?
Apr 13^th, 2009, 12:08am

hi all

i have a puzzle about the phase noise simulation for the circuit consist of both autonomous and driven circuits. for example, VCO (crystal oscillator) followed by a buffer, the oscillator can not generate the full swing signal, the buffer is used to convert the small swing to CMOS level. Can we run the pnoise simulation combining VCO and the buffer together? can the phase noise at the buffer's output represent the total phase noise? or we must simulate the two respectively?
i run a test for a vco+buffer(run pnoise together), the phase noise at the vco's output seems almost the same with the phase noise at the buffer's output, can I tell " the noise in the buffer has little influence for the total circuit? but if i simulate the buffer alone with a sinewave stimulus( i get the amplitude and frequency from the VCO's simulation, and the PNoise is timedomain), the buffer's phase noise is in the same order with the VCO's phase noise, from this, i think the noise in the buffer can not be neglected, so i have a puzzle, which is the correct way to simulate the circuit with both autonomous and driven componets?

regards

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Andrew Beckett

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Re: how to run pnoise simulation of oscillator + buffer?
Reply #1 - Apr 13^th, 2009, 2:07pm

pancho_hideboo wrote on Apr 13^th, 2009, 8:08am:

I can't find out any puzzle.
If any, your sentences themselves are puzzles because they are very difficult to read and understand.

Separation of VCO and Buffer is no more than your partitioning. Other people might separate VCO and Buffer as different partitioning from you.
Even if you connect something which you think as buffer to VCO, VCO+Buffer is no more than VCO, that is, autonomous circuit. That is not driven circuit at all.

You have to learn measurements using actual instruments. Not "EDA Tool Play".

Most of Cadence Tool Players have no experience of actual measurements.
Maybe this is also true for you.
If you have have experience of actual measurement, you never confuse such basic issues.

Pancho Hideboo,

Do you really have to be so rude and intolerant all the time? It actually makes it very hard to offer constructive advice to the original requestor when you're so confrontational.

We all have to be aware that not everyone has perfect English (including me, and I am English!). Also that not everyone has as much experience as others (otherwise they probably would not be asking questions) - every one of us is learning (hopefully) all the time as we gain experience.

Also you keep making completely unfounded statements such as "Most of Cadence Tool Players have no experience of actual measurements". I cannot see how you can possibly know that - it's not my experience of Cadence users and I almost certainly interact with many more of them than you do. (BTW, "Cadence Tool Players" is rather strange terminology - if somebody else had said something like that, you'd be pulling them up for not using recognised terminology!).

Even if you are familiar with measurement, using a circuit simulator is somewhat different from measurements in the lab - there are things you can do with the simulator which cannot be done in the lab (and vice versa), so it is reasonable that there are things that are not always obvious.

It sounds as if Franco is simulating with timedomain mode of pnoise - but it's not obvious how that is being used to compute the Phase Noise.

Franco, as Pancho Hideboo eventually said (after chastising you for not being as clever as he is), can you outline precisely how you're making the measurements with the two cases, and then we might be able to help you more with your problem.

Best Regards,

Andrew.

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franco

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Re: how to run pnoise simulation of oscillator + buffer?
Reply #2 - Apr 13^th, 2009, 10:19pm

Hi Pancho and Andrew,
Thank you for your reply firstly. Yes, my english is poor, i am learning english to improve my communication skill with english now. so i'll try my best to describe the question again as clear as possible.
The question is shown below, a VCO followed by a buffer, the buffer is used to convert the small voltage swing at node "a" to CMOS swing.
--------- ---------
| |__a___ | buf |___ b
| vco | | |
--------- ---------
I run 3 Pnoise simulations
1) in PSS setting, check on the "Oscillator" box, select node "a" as Oscillator node. In Pnoise setting, select node "a" as the output, Noise type is "sources", Sweeptype is "relative" Maximum sideband is 10. after simulation, i can plot the phase noise L1(f).
2) in PSS setting, check on the "Oscillator" box, select node "b" as Oscillator node. In Pnoise setting, select node "b" as the output, Noise type is "sources", Sweeptype is "relative" Maximum sideband is 10. After simulation, I can plot the phase noise L2(f).
3) remove the vco, only buf is simulated. Based on the previous simulation, i record the frequency and amplitude at node "a", and in this simulation, i use an ideal sinewave with the same frequency and amplitude as the input of the buffer. I treat it as a driven circuit, in PSS setting, DO NOT check "Oscillator" box, in Pnoise setting, Noise type is "jitter", Sweeptype is "absolute" select node "b" as the output. Maximum sideband is 10. After simulation, plot the output voltage noise Sn(f) firstly, then calculate Sphi3(f)=[2*pi*f/SR]^2*Sn(f), SR is the slew rate at the threshold value. L3(f)=10*log10[Sphi3(f)/2].
Now, if i want to get the total phase noise including the VCO and the buffer, I have two thoughts, A) Case 2's simulation results is the total phase noise. B) using L1(f) to calculate Sphi1(f), than plus the Sphi3(f), the final result is L(f)=10*log10{[Sphi1(f)+Sphi3(f)]/2}.
which is correct? if both are wrong, Could you give me some advice how to simulate this kinds of circuit?
thanks

Franco

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rfmems Senior Member Offline Posts: 121	Re: how to run pnoise simulation of oscillator + buffer? Reply #3 - Apr 15^th, 2009, 12:34am Hi Franco, I think (2) is OK, (3) might also work but you don't need to do that since (2) is good enough.
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ywguo

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Re: how to run pnoise simulation of oscillator + buffer?
Reply #4 - Apr 15^th, 2009, 10:30pm

Hi Franco,

I would choose your solution 2) because it is easy and correct totally. Solution 1) is wrong in theory. However, probabley L1(f) is near L2(f) because the buffer does not contribute the phase noise as much as the oscillator. As to solution 3),
Quote:

L(f)=10*log10{[Sphi1(f)+Sphi3(f)]/2}

is it reasonable to sum the Sphi1(f) and Sphi3(f)?

Yawei

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franco

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Re: how to run pnoise simulation of oscillator + buffer?
Reply #5 - Apr 16^th, 2009, 2:14am

Hi Yawei and chenyan
Thank you!
Yes, 2) is simple and easy to do when runing simulation, but I think only noise in the buffer at the threshold crossing is useful for the total phase noise, the noise in the buffer when the ouput is High or Low is useless for the total phase noise, so if I use simulation 2) as the result, I over-estimate the phase noise, that is, if 2)'s result can meet my spec, the circuit must be OK, is this thought right? would you like give more explanation about this?
The noise in the VCO and the noise in the buf are independent, so I think the phase noise(before 10*log10) can be summed directly, but one thing I am uncertion is, the two Sphi1(f) and Sphi3(f) are simulated in different Pnoise setting, one is "source" and the other is "jitter". That is Sphi3(f) is the sampled phase noise at the threshold crossing, but Sphi1(f) is not, so, i am not sure are the sum is meaningful?
Let us recall the phase noise model of the PLL, generally, we simulate the phase noise of VCO, CP, DIV etc independently, then after their transfer function respectively, at the output, we add the phase noise together, useing the final summed phase noise, we can calculate the total PLL's jitter. in the PLL's model, the DIV (divider) is a driven circuit, and we should use "timedomain" or "jitter" when simulating it, for other components, we should choose "source". I think it is a little similar to the question I asked, when we sum the phase noise together, is it meaninful?
Besides, consider a PLL with input 50MHz, and output 500MHz, the divider ration is 10, assuming only VCO and DIV are noisy componets, the the transfer function of VCO is Hvco(f), the DIV tranfer funtion is Hdiv(f). the VCO's phase noise is Svco(f) and DIV's phase noise is Sdiv(f). If the frequency range what i am interesting is 1K~100M. Since I simulate DIV with "jitter" option, so the valid frequency range is 1K~25MHz. Now I want to calculate the PLL's output jitter. firstly, I can calculate the phase noise of the PLL as
Spll(f)=Svco(f)*Hvco(f)^2+Sdiv(f)*Hdiv(f)^2
than i integrate the Spll(f) to calculate the jitter. Now, the question is how to choose the integartion frequency range?
1) integrating Spll(f) from 1KHz to 100MHz.
2) integrating Svco(f)*Hvco(f)^2 from 1KHz to 100MHz, and integrating Sdiv(f)*Hdiv(f)^2 from 1KHz to 25Mhz then sum them.
which is correct?

Regards
Franco

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rfmems

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Re: how to run pnoise simulation of oscillator + buffer?
Reply #6 - Apr 16^th, 2009, 8:36am

Hi Franco,

If your circuit is only VCO+buffer. Then pnoise simulation with 'sourses' is the right way to go.

When you talk about pll, it is different story. Here strobed pnoise simulation is used, as the noise except the threshold will not be seen by the VCO. But that is only a method to simulate. You can not meausre the strobe noise with you real chip.

When you measure your VCO+buffer, you see the noise close to your simulation with pnoise 'source'.

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franco New Member Offline Posts: 4	Re: how to run pnoise simulation of oscillator + buffer? Reply #7 - Apr 27^th, 2009, 9:32pm Hi rfmems thank you for your kindly reply! Franco
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