I don't remember all the details but I think there was a presentation of some such device from ST at one conference. I think they called it FinFET and it has gates on both sides, above and below. What I don't remember is how they made the second gate. You might want to check it out.

By the way, you may double the number of wafers on both sides but you will also increase the processing costs enormously, atleast by factor 2x and probably more if you could do lithography on both sides. And you would need to punch vias through the wafer which is usually around 700 um thick to connect both sides. Plus packaging the die would be a big headache. You would need to atleast have all bond pads on one side of the die, and there would be possibly other issues such as mechanical and thermal robustness.

Nonetheless, I don't think it is impossible. The question is probably if it is useful or if equal amount of benefits cannot be realized by other, cheaper means.

Regards,

Vivek

Vivek, I agree with Rob. I think what you describe is an double-gate transistor. I am also sure that ST is doing research on that as double-gate transistors (better control of channel) are seen as the solution to smaller feature sizes.

Patterning on the back of wafers is quite common for through wafer VIAS that are used to stack chips on top of one another. Using the backside for actual circuitry would be difficult as many wafer handling systems use a vacuum chuck that would crush the layers beneath the susceptor. Also, the backsides of the wafer are often doped differently from the front side for defect gettering purposes.

to the best of my knowledge putting transistors on both side of the wafer is not done for a number of reason -

Interactive lithography - the litho steps that include thermal cycles would affect both sides of the wafer, making for some interesting foundry process definitions.

Defect density - Now you got to get both sides to work and if one side is dead, then you toss the whole things.

Physical preparation - The cleaning, planarizing and polishing to prep wafer side needs a physical mount to do. Until the final passivation layer gets put on a wafer (hard and very tough to scratch) the lower levels can have some soft and easily damage pieces (think soft copper or older metal aluminum interconnects)

Connections thru the wafer in the form of interconnect vias has been done, but I am not sure how much it gets used right now.

Stacked chips are a pretty common thing right now in SIP (system in package) things.

Fin-FETS and other 3D transistors have been around for a while now in R&D but these are built up on one side of the wafer. Also multi layer structures with transistors stacked on top of each other have also been an R&D thing for a while but have not generated too much commercial interest, because the fabrication process is messy and expensive.

State of the art CMOS is at 13 atoms channel length and 4 atoms gate oxide thickness. Classic CMOS geometry scaling is coming to an end. (But havent we been saying that for the last 10 years?)