to the best of my knowledge putting transistors on both side of the wafer is not done for a number of reason -
Interactive lithography - the litho steps that include thermal cycles would affect both sides of the wafer, making for some interesting foundry process definitions.
Defect density - Now you got to get both sides to work and if one side is dead, then you toss the whole things.
Physical preparation - The cleaning, planarizing and polishing to prep wafer side needs a physical mount to do. Until the final passivation layer gets put on a wafer (hard and very tough to scratch) the lower levels can have some soft and easily damage pieces (think soft copper or older metal aluminum interconnects)
Connections thru the wafer in the form of interconnect vias has been done, but I am not sure how much it gets used right now.
Stacked chips are a pretty common thing right now in SIP (system in package) things.
Fin-FETS and other 3D transistors have been around for a while now in R&D but these are built up on one side of the wafer. Also multi layer structures with transistors stacked on top of each other have also been an R&D thing for a while but have not generated too much commercial interest, because the fabrication process is messy and expensive.
State of the art CMOS is at 13 atoms channel length and 4 atoms gate oxide thickness. Classic CMOS geometry scaling is coming to an end. (But havent we been saying that for the last 10 years?)