I design a fractional-N pll,boss said that the lock time should be control in 20us,but see from the simulation,the result is not fine.the plot shown have some problems,but my topic focus on the PFD circuit.
My PFD is the conventional 2 dff+feedback,I think that this type PFD only can discriminate phase in a word ,many book describe it can discriminate frequency,but its principle is still begin from phase.
Now my wish voltage is 1v,the simulation show that the ref and feedback signal is almost  reversed(means these two signal' frequency are same but phase diff pi@that time)near 1V,but the voltage is still up!because the PFD see it as phase difference,so I wonder is there any way could help me realize frequency discriminate at my 1V? If done,the system could lock fast........
Thank you

[quote author=raja.cedt link=1245228641/0#1 date=1245233216]hi,
  In your waveforms whats that under damped waveform? i guess it is control node voltage..

Hi,3Q first!
 Do you mean my damp is very small,so the wave is oscillating? YES,maybe my damp is not so large enough,but if my PFD could detect the frequency immediately,then the wave should be small ,and the lock time alse shorts, is that right?