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icekalt Community Member Offline Posts: 36 Aalen, Germany	comparator problem Jun 24^th, 2009, 6:02am hello, I have simulated my comparator circuit and the result is strange. I didn't get what expected. My output doesn't change when there is difference between input voltages. Can someone gave me hints on this?
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icekalt Community Member Offline Posts: 36 Aalen, Germany	Re: comparator problem Reply #1 - Jun 24^th, 2009, 6:03am here is the simulation waveform
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raja.cedt

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Re: comparator problem
Reply #2 - Jun 24^th, 2009, 6:16am

hi
can you please post output at the cross coupled load..becasue that is the critical one..and i was surprised with your first stage output..many spikes are coming in the output, what we are expecting is some common mode with sine wave..but how spikes are coming, can you please simulate and see and whats your clock frequency?

Thanks,
rajasekhar.

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HdrChopper Community Fellow Offline Posts: 493	Re: comparator problem Reply #3 - Jun 24^th, 2009, 7:03pm Hi, Have you checked whether the voltage swing on the gate of your output inverters is large enough to guarantee you hit the inverters threshold? You might eventually need a level shifter in that stage... Regards Tosei
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icekalt

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Aalen, Germany

Re: comparator problem
Reply #4 - Jun 25^th, 2009, 7:28am

raja.cedt wrote on Jun 24^th, 2009, 6:16am:

hi
� can you please post output at the cross coupled load..becasue that is the critical one..and i was �surprised with your first stage output..many spikes are coming in the output, what we are expecting is some common mode with sine wave..but how spikes are coming, can you please simulate and see and whats your clock frequency?

Thanks,
rajasekhar.

thx for the reply rajasekhar. Here is the waveform in attachment. Vout+ and Vout- are the output of cross coupled latch. The frequency of the clock is 1MHz. I have been simulating but until now still didnt find the solution.

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output_of_latch_and_clock_001.GIF

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icekalt

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Aalen, Germany

Re: comparator problem
Reply #5 - Jun 25^th, 2009, 7:33am

HdrChopper wrote on Jun 24^th, 2009, 7:03pm:

Hi,

Have you checked whether the voltage swing on the gate of your output inverters is large enough to guarantee you hit the inverters threshold?
You might eventually need a level shifter in that stage...

Regards
Tosei

thx for the reply the chopper. You can check previous post with the output of the cross-coupled latch. The voltage at the gate of inverter M17 and M16 is around 3V(see Vout+). So i think that should be ok.

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subgold Community Member Offline Posts: 97	Re: comparator problem Reply #6 - Jun 25^th, 2009, 11:16am the output of your preamp has a voltage level around 1.8V, but your clock signal goes only up to 0.8V, which is not able to turn on the NMOSs M7 and M8. I am afraid your comparator is always off.
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icekalt

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Aalen, Germany

Re: comparator problem
Reply #7 - Jun 25^th, 2009, 3:14pm

subgold wrote on Jun 25^th, 2009, 11:16am:

the output of your preamp has a voltage level around 1.8V, but your clock signal goes only up to 0.8V, which is not able to turn on the NMOSs M7 and M8. I am afraid your comparator is always off.

subgold, i changed my clock to 3.3 voltage but i still didn't get the desired output..look at the new attachment

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output_of_latch_and_clock.GIF

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nobody

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Re: comparator problem
Reply #8 - Jun 26^th, 2009, 12:22am

You use a double-latch, which can improve the metastablity,and it is weird you have that waveform. Basically, I am with Tosei . Maybe the gain is not big enough to trigger a double-latch. During one phase when CLK=1, M4,M5 and M11 are on. The Ron of M11 is too small, which is low gain equivalently, to trigger the latch. So try to reduce the size of M11 to increase the Ron and improve your gain. Or you
can use a latch in your first preamp to boost the gain by 4 or more.

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icekalt

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Aalen, Germany

Re: comparator problem
Reply #9 - Jun 26^th, 2009, 12:46am

nobody wrote on Jun 26^th, 2009, 12:22am:

You use a double-latch, which can improve the metastablity,and it is weird you have that waveform. Basically, I am with Tosei . Maybe the gain is not big enough to trigger a double-latch. During one phase when CLK=1, M4,M5 and M11 are on. The Ron of M11 is too small, which is low gain equivalently, to trigger the latch. So try to reduce the size of M11 to increase the Ron and improve your gain. Or you
can use a latch in your first preamp to boost the gain by 4 or more.

Can you give me some example or link to show is latch applied in preamplifier?

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raja.cedt Senior Fellow Offline Posts: 1516 Germany	Re: comparator problem Reply #10 - Jun 26^th, 2009, 12:51am hi, your first stage results are wrong...check got dc bias because you are getting spikes in the o/p thanks, Rajasekhar.
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icekalt

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Aalen, Germany

Re: comparator problem
Reply #11 - Jun 26^th, 2009, 1:19am

raja.cedt wrote on Jun 26^th, 2009, 12:51am:

hi,
� �your first stage results are wrong...check got dc bias because you are getting spikes in the o/p

thanks,
Rajasekhar.

i just replaced the PMOS load in the preamplifier with resistive load. Now it's getting better but i still got the spikes. When i simulate only the preamplifier(other part is removed), then there is no spike at the output of preamplifier. M5,M6,M7 and M8 maybe the cause?

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waveform_comparator_002.GIF

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nobody

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Re: comparator problem
Reply #12 - Jun 26^th, 2009, 2:14am

As a method to increase the gain in preamp stage, you can use a cross-coupled pair to do that. The gain was gm,input/gm,pmos. Now the gain is gm,input/(gm,pmos-gm,cross-coupled).

Another method is to increase the Ron of M11, which stores the voltage difference and kind of resets the output voltage, and you can see page 263
on Design of High-Speed Communication Circuits by Ramesh Harjani.
Just use books.google.com to find that book. The gain is gm1*(0.5Ron,12||(-1/gm4)) where -1/gm4 comes from a cross-coupled pair or a latch . Make sure the overall gain is positive. In your case, you have one Ron and an equivalent resistor from two latches. Therefore, Ron is parallel with PMOS and NMOS latches at the same time. That is complicated for me to derive the gain. Maybe you can try a method like Fig.4 on page 263. http://books.google.com.tw/books?id=wWeJYKiPoZQC&pg=PA263&lpg=PA263&dq=introduct...

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subgold

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Re: comparator problem
Reply #13 - Jun 26^th, 2009, 3:12am

icekalt wrote on Jun 26^th, 2009, 1:19am:

raja.cedt wrote on Jun 26^th, 2009, 12:51am:

hi,
� �your first stage results are wrong...check got dc bias because you are getting spikes in the o/p

thanks,
Rajasekhar.

i just replaced the PMOS load in the preamplifier with resistive load. Now it's getting better but i still got the spikes. When i simulate only the preamplifier(other part is removed), then there is no spike at the output of preamplifier. M5,M6,M7 and M8 maybe the cause?

the spikes are due to the gate parasitics of the next stage. i think that is OK.

but M11 seems to be for reset purpose, then shouldn't it be a PMOS or controled by _CLK?

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icekalt

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Aalen, Germany

Re: comparator problem
Reply #14 - Jun 26^th, 2009, 5:46am

subgold wrote on Jun 26^th, 2009, 3:12am:

icekalt wrote on Jun 26^th, 2009, 1:19am:

raja.cedt wrote on Jun 26^th, 2009, 12:51am:

hi,
� �your first stage results are wrong...check got dc bias because you are getting spikes in the o/p

thanks,
Rajasekhar.

i just replaced the PMOS load in the preamplifier with resistive load. Now it's getting better but i still got the spikes. When i simulate only the preamplifier(other part is removed), then there is no spike at the output of preamplifier. M5,M6,M7 and M8 maybe the cause?

the spikes are due to the gate parasitics of the next stage. i think that is OK.

but M11 seems to be for reset purpose, then shouldn't it be a PMOS or controled by _CLK?

the comparator i used actually that one from uyttenhove. M11 should be NMOS and controlled by CLK. I attach that article from IEEE for you. Thx..

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A_CMOS_6-bit_1_GHz_ADC_for_IF_Sampling_Applications.pdf

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