The Designer's Guide Community
Forum
Welcome, Guest. Please Login or Register. Please follow the Forum guidelines.
Mar 22nd, 2023, 10:13am
Pages: 1
Send Topic Print
Simulating the input-referred noise of a SC integrator (Read 2110 times)
analog_ali
New Member
*
Offline



Posts: 3

Simulating the input-referred noise of a SC integrator
Sep 28th, 2009, 10:00pm
 
Hi,

I would like to simulate the input-referred noise of a SC integrator in SpectreRF:

- My test bench is the same as the circuit depicted in figure 10, on page 12 of (http://www.designers-guide.org/Analysis/delta-sigma.pdf), where S/H is implemented by ideal circuit elements (ideal switch + cap + buffers) to avoid hidden states)

- I am using the "time-domain" noise feature of spectreRF as suggested by: (http://www.designers-guide.org/Analysis/sc-filters.pdf) to simulate the discrete-time behavior.

- to calculate the noise power I integrate the spectrum from 0 to fs/2.

My main question is: How is it possible to obtain the "input-referred" noise from this "time-domain" noise simulation, as it only allows to plot (and integrate) the "output" noise? (in Cadence: DirectPlot >> main form >> tdnoise).

Also, I am not sure whether the "input-referred" noise means the noise across the sampling cap or it is just the noise at the input voltage source node to the integrator?


Any help is very much appreciated!

Thanks,
Ali

Back to top
 
 
View Profile   IP Logged
Pages: 1
Send Topic Print
Copyright 2002-2023 Designer’s Guide Consulting, Inc. Designer’s Guide® is a registered trademark of Designer’s Guide Consulting, Inc. All rights reserved. Send comments or questions to editor@designers-guide.org. Consider submitting a paper or model.