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Simulating the input-referred noise of a SC integrator (Read 2203 times)
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Simulating the input-referred noise of a SC integrator
Sep 28th, 2009, 10:00pm

I would like to simulate the input-referred noise of a SC integrator in SpectreRF:

- My test bench is the same as the circuit depicted in figure 10, on page 12 of (, where S/H is implemented by ideal circuit elements (ideal switch + cap + buffers) to avoid hidden states)

- I am using the "time-domain" noise feature of spectreRF as suggested by: ( to simulate the discrete-time behavior.

- to calculate the noise power I integrate the spectrum from 0 to fs/2.

My main question is: How is it possible to obtain the "input-referred" noise from this "time-domain" noise simulation, as it only allows to plot (and integrate) the "output" noise? (in Cadence: DirectPlot >> main form >> tdnoise).

Also, I am not sure whether the "input-referred" noise means the noise across the sampling cap or it is just the noise at the input voltage source node to the integrator?

Any help is very much appreciated!


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