can anybody explain how breakdown voltage varies in si and SiGe bulk CMOS transistors...

and BD voltage importance in analog applications...

Breakdown across a reverse biased junction behaves as follows:

V_BV ≈ E²_crit.ε_si(N_a+N_d)/(2.q.N_a.N_d)

where ε_si=1.04E-12 F/cm
N_a is acceptor doping atoms/cm³
N_d is donor doping atoms/cm³
q is electronic charge
and the critical electric field across the junction E_crit is between 1E5 and 1E6 v/cm in Silicon.

It is really just a way of defining when a reverse biased junction fails catastrophically. However the breakdown value itself is not so important as any design that allows the electric field across a junction at or beyond E_crit is doomed to fail anyway. A more important concern is what happens before reaching E_crit when there is significant leakage current across the junction.
If we define the breakdown voltage as that voltage where the junction leakes 10 nAmps, then there are voltages below this where the junction leaks say 1nAmp or 100pAmps. This may seem low but this can have two effects:
One is, over time, such a stressed junction will deteriorate and eventually (prematurely) fail. An example of this would be ringing when switching, when the junction could be stressed for a very short time. But over time....
But second may be that two matched devices, one currently more stressed than the other, will no longer be matched as expected because of this leakage current.