i am confused how to setup simulation to get gm/ID vs ID/W graph.
in Mr.Murmann's lecture notes, he use single nmos which its drain and gate isn't connected each other. he uses about VDD/2 for VDS voltage and runs dc simulation for variable VGS voltage. FYI, I found different result for different VDS voltage.
On the other hand, in Ashutosh Tiwari's lecture notes, he also runs dc simulation for variable VGS voltage but with drain terminal connects to gate terminal, which ensure the device remains in saturation region.
which one is correct?
**please refer to :
http://discovery.bits-pilani.ac.in/discipline/eee/agupta/microelectronic-circuit... for Ashutosh Tiwari's lecture notes.
I run a simple simulation, in which the drain voltage and gate voltage are swept. Gm/Id for nmos and pmos are ploted and attached here. It is 0.13um CMOS process, 1.2V nmos and pmos. Gm/Id curves keep almost constant unless VD (drain-source voltage) becomes near zero. It means that this method is applicable in almost all operating regions. So both method can get good enough results to let the designers make their choices. Please remember that such the drain-source voltage usually is not equal to the real value when the transistors are used in OPAMP and the above results are good enough.
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