ORNITORINCO
New Member
Offline
Posts: 5
|
Hello everyone,
I am trying to simulate my PLL top level schematic in Cadence ADE (Analog Design Env). Along with verilog-a and spectre models devices I have a verilog-HDL sigma-delta modulator module. Being the sdm a mash 1-1-1 architecture, it embeds 3 first order modulators as building blocks plus the output noise-canceling network. Each one of these sub-blocks has an input reset port, and all these ports are tied together using a wire in the top level verilog file. The sdm block compiles and run correctly using the digital simulator ncsim and simVision.
When compiling in ADE (using ams simulator), I get the following error from ncelab:
********** .reset(reset), | ncelab: *E, CUVPOM (./inhl/verilog_fb/sdm_mash3/module/verilog.v,26|11): Port name 'reset' is invalid or has multiple connections. **********
Anyone can help with this issue?
Thanks.
|