greetings,

so, my question is:  what is the best way to reduce clock jitter and distribute my clock?  there are a few jitter cleaners out there, but I would like some expert advice before I go any farther.

background:
I am attempting to build a software defined radio as a personal project, but I am fairly new to the subject.  I have been doing a lot of research and hitting the forums at National Semi, and TI for info.  from that, I have come up with a basic design concept, which is based on this eval board:
http://www.national.com/pf/AD/ADC14155.html#Boards

my design is basically that eval board, with a SAW filter in the frequency I want (460mhz +/-20), a antenna connector, and a clocking circuit.

I want my clocking circuit to be capable of being distributed to both the ADC and my FPGA (virtex 2pro) board via the SMA clock input.  I want to run the clock at 100mhz.

also, do you think it would be worth buying a $180 oscillator with +/-30 parts per billion error?  I am not sure how to best spec a oscillator for this application.

Thanks much!