In the input offset storage technique in comparators for offset cancellation, there are capacitors at the inputs of the comparator. While designing a comparator for the same, how can we maintain our dc bias voltage at the gates of the input transistors, with capacitors placed at the gates??

Re: In designing a comparator with input offset cancellation technique, we need to design switches. There are three switches: one connecting the input to output(unity gain feedback), second connecting the input to reference voltage and third connecting to the inputs to be compared.
Out of these three the first is placed to the right plate of the capacitor and the other two to the left of the capacitor near the inputs.
While designing the amplifier we do the dc analysis and adjust the dc voltages. After obtaining these values, when a capacitor is introduced at the inputs, as soon as the switch for the feedback is connected, due to some leakage current through the switch(transmission gate), the capacitor acquires some charge at the right plate near inputs and settles on to that dc value changing the operating points.
How should I avoid these leakage currents????

This is charge injection -- I wouldn't call it "leakage current".  The switches turning on/off dump charge into the inputs of your comparator.

You can reduce the effect of this by

1)  using smaller switches
2)  larger input capacitor
3)  larger input devices in your comparator