The Designer's Guide Community
Forum
Welcome, Guest. Please Login or Register. Please follow the Forum guidelines.
Jun 30th, 2022, 11:51am
Pages: 1
Send Topic Print
troublesome task regarding analog verification (Read 3566 times)
descanso
New Member
*
Offline



Posts: 1

troublesome task regarding analog verification
Nov 10th, 2010, 9:24pm
 
Hello,

I am very interested in the analog verification discussed here.
I am wondering how would you do my troublesome problems.
It would be grateful to hear your opinion and experience.

1. I used to do mixed-signal chip level verification by making behavioral
model of analog blocks with verilog-HDL. I would like to start modeling
by verilog-AMS for more complex design.
Co-simulation of RTL and verilog-AMS is possible in my design
environment, but users do not have that. In this case, both behavioral
model described in verilog and that described in verilog-AMS are needed,
because users need the chip model described in verilog to verify their
system. I guess it would bother me.

2. It will be helpful to see spectrum in frequency domain quickly.
However I have to dump data and transfer the other FFT tool.
Do you know the easy way to do FFT with NCverilog?

3. It is possible to pass/fail judge by comparing the simulated data
with the expected data in digital verification. But it is needed to
check wave forms again and again when real value is used in the
behavioral model. How do you address this messy work?
Back to top
 
 
View Profile   IP Logged
jbdavid
Community Fellow
*****
Offline



Posts: 377
Silicon Valley
Re: troublesome task regarding analog verification
Reply #1 - Nov 10th, 2010, 11:34pm
 
There is a lot of good material on both modeling and verification in the paper archives at http://www.bmas-conf.org .

I of course have been suggesting that this field is crucial to the future of most SOC development.. Steve Leibson of the eda360 insider blog http://eda360insider.wordpress.com is reporting some interesting developments in this area as well.

However it a forum such as this is a poor vehicle in which to give an overview.

I will say that testbench and instrumentation development for the design and automating the results are twice the work of actually writing the models, so you should keep that in mind when staffing your project.

If you are getting started with this, I recently discovered that a decent set of (open source) ic design tools are included in the "free electronics lab" spin of Fedora (the fedora-FEL spin) that is only a 1.3G live dvd download, ready for you to install.
for analog verification tools include ngspice, icarus verilog and gnucap , as well as enhancements to Eclipse to support both verilog and vhdl editing.

good luck!

Back to top
 
 

jbdavid
Mixed Signal Design Verification
View Profile WWW   IP Logged
Pages: 1
Send Topic Print
Copyright 2002-2022 Designer’s Guide Consulting, Inc. Designer’s Guide® is a registered trademark of Designer’s Guide Consulting, Inc. All rights reserved. Send comments or questions to editor@designers-guide.org. Consider submitting a paper or model.