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nanosim memory design (Read 2719 times)
seahs
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nanosim memory design
Nov 15th, 2010, 7:47pm
 
how to calculate the sram bitline wiring capacitance ?

It seems the total bitline cap is very small in my design, about 100fF for a bitline with 1024 memory cells connected in 130nm. I am wondering if the metal layer cap is included.

Thanks for any suggestion.
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