Quote:The PLL and digital circuit share the same regulator and the regulator can be bypassed.
Bad, bad idea to use same regulator for analog vdd of the oscillator & digital soc cktry outside pll.
Watching the supply profile, & assuming digital cktry is not working exactly at 1.3 GHz, the supply profile seems to be dominated by VCO current itself.
Quote:Is the regulator working properly ?
Yes, the regulator works properly.
Quote:Is the chosen o/p bypass cap value enough to tolerate vco supply current profile ?
Yes, the o/p bypass cap is big enough to tolerate supply current profile.
Quote:Has the VCO supply current profile changed from wot the ldo was designed for ?
No way to measure the VCO supply current profile. But the chip current consumption doesn't change from what we designed for.
Localize the jitter source -- if it's from power suplpy ripples due to digital cktry operation, then try n manage with the bypass cap.
Quote:If not possible, then go for a separate ldo for pll.
Yes, one of our plan is to separate the power supply of PLL and digital circuit and only the PLL use that regulator.
Quote:One reason I think is that it is due to the ESL of the decoupling cap connected between the power and ground
Quote:Havent seen ESL playin such a big role so as to be noticeably this large in on-chip caps. If it's off-chip, definitely check ESL, & try n fit these ripple magnitudes with ESL value obtained. if it fits, could explain these inductive voltage peaks.
The caps are off-chip.
--Mayank.