Hi folks,

I am designing a fully differential OTA used in a switched capacitor (SC) integrator. I want to use an SC CMFB for the OTA.

I wonder if I should use a much faster (say 4x faster) clock for the CMFB than the clock for the integrator, since the CMFB needs a few clock cycles to settle to the desired common-mode voltage.

I checked quite a few papers, but found no one mentioning the clock speed for the CMFB.

Thank you all in advance.

Leon

Hi Rakesh,

Thank you for your reply. Assume we use the same non-overlap clocks for both CMFB and the integrator. Assume PHI1 is for sampling and PHI2 is for integrating.

The OTA only needs to be available in PHI2. But the question is if the common mode of the OTA can settle fast enough to the desired value within PHI2?

Leon

i doubt if it is a good idea.

provided ur targeted common mode voltage is fixed and not changed at every cycle, then the problem you mentioned is more like a startup issue. once it settles to the desired common mode level, the SC CMFB will hold it and will not change any more, because theoritically there will be no more charge/discharge happening in the lossy integrator formed by the SC CMFB.

from a practical point of view, how do you obtain the 4x clock? it could be very costly. if you already have such a clock available, then why not use it to enhance the performance of the SC integrator itself?