loose-electron wrote on Apr 18th, 2011, 11:36am:Intuitive explanation? - A larger portion of the current thru the transistor passes thru the silicon away from edges of the transistors. The catch-release of the electron/hole is less when not along the edge of a junction.
Jerry,
That doesn't sound quite correct to me. If I recall, 1/f noise in MOSFETs is due to carrier trapping at the Si-SiO2 interface. That's where most of the traps are, not so much at the P-N junctions created at the S/D implants. The surface-dominated behavior of 1/f noise is one of the reasons why bulk devices such as JFETs or BJTs show very little 1/f, which was also true for PFETs in older technologies using buried channels.
A larger gate area will lead to an ensemble averaging of the trapping behavior. In other terms, if you are sending the same amount of current through a larger gate, then the carriers are likely to get stuck in many different, independent traps on their way home. For very tiny devices, you may be unlucky enough to get one single trap which looks rather nasty. I think there's an illustration in Tsividis' book.
Regards,
Vivek