Hi, RobG
   There does not exist this dip phenomena in other Foudry Lib.  Maybe it is modelling issue.

zwtang
2011/5/14

RobG,

Most likely this is due to quasi-static modeling. When the transistors turn on, some (positive) charge is sucked from the drain/source, dipping their potential. This takes some time, but, in quasi-static models, it is instantaneous. The time is ~ 1/omega_T of the transistor. My guess is that this is a quasi-static model and the instantaneous drain of the entire charge from node 'a' makes it dip a lot.

omega_T (gm/Cgs) = 3/2*mu*(VGS-VT)/L^2 turns out to be ~ 10^7 rad/s for L=25um (assuming mu=100cm^2/V/s, VGS-VT=1V---all rough numbers). This gives 1/omega_T ~ 100ns. For a 50ns ramp, the charge buildup is definitely not quasi-static.

The one with the series connected transistors is likely more accurate, as their omega_T is 8^2=64 times higher. I guess you can split it into more and more pieces and see when the results (at the appropriate corresponding nodes) become consistent.

Cheers
Nagendra

Thanks nrk1, I knew nothing about that effect.  That quirk would explain what I'm seeing. I found a little documentation: http://nikola.com/pdf/bsim3ch5.pdf . The models are BSIM3v3 and the documentation says they are NQS, but I do not see the NQSMOD parameter in the model file so I assume the documentation is incorrect as it appears the default is QS (true?).

Like you predicted, the effect worsens if I make the PMOS longer and goes away if I put a bunch of short channels in series. I've also since found that I get the same effect if I replace the "bottom" PMOS with a diode connected NMOS, so I'm guessing the rectifying property of the circuit prevents the charge you are talking about from going anywhere.

Is this effect real at all? I can see how Cgd could couple the voltage ramp to the drain, but can't see how any voltage amplification could take place. In addition, when I put a cap there the effect was moderated considerably.

Questions:

Same results using a DC sweep instead of a transient model?

Model type ? (BSIM ??)

Specific Foundry process (TSMC 90nm?)

Discontinuty problems existed in a big ugly way with the older transistor models.

Also, runa set of bias curves on the transistors thru the op points shown (Vgs, Id, Vds) and see if anything is seen there.

fair enough, just asking the questions....

Lex wrote on May 18^th, 2011, 4:18am:

I'm glad someone caught that. BTW, my original comment on the natural NMOS models is related to this point: I don't trust any model no matter how much data is used to back the Vt and mobility values: a good design is insensitive to those parameters and as this post shows, there are often bigger issues with the model itself.

[quote author=Alexander link=1305327527/0#12 date=1305788371]RobG wrote on May 18^th, 2011, 8:24am:


Alaxander, you have picked one of the few circuits that really matter, and it really has nothing to do with whether a natural device is poorly modeled compared to a normal device.  Nowadays most of the problems are layout dependent, not because the nominal Vt is 50mV off. If you need a lot of history to get accurate models you have to ask yourself what is going on. Incompetent modeler? Unstable process? Are things going to be better because you are using a normal NMOS instead of a natural for a cascode or diff pair? No, those are other issues. Man up as the say, we've been designing with crappy models for decades . People design across currents and device sizes that vary by orders of magnitudes. The models can't be accurate over that sort of range. On top of that, they have their inherent quirks (like above).

Anyway, as someone who made a career out of fixing other people's bandgaps I can tell you most of the time the person who created the models are blamed when it is the designer's fault. They run the diodes at too high a current density so poorly controlled effects dominate. Or the system is too sensitive to mismatches. Or they match the wrong resistors, or they decide that since it doesn't have to be "that accurate" they can cut corners only to find some effect they didn't think of creeps in. The way to deal with poorly modeled new-process bipolars in a bandgap is to add trim, and to design in a region where the model will give consistent results, and realize that the "magic voltage" magnitude may not be exactly where the simulation says it is.

That's my experience anyway,
Rob