Hi,

When I do netlisting of av_extracted view of RC extracted layout. Aspect ratio of transistor is matching with schematic design. I mean, sizing of circuit (schematic) in netlist is not reflecting in extracted netlist. some time, if two device are in cascode position then, upper one's aspect ratio is reflected in lower one's size.

I do not where exactly going wrong? I believe it must be with model files. I am not sure about it.

Please, let me know your opinion and solution.

I would appreciate it.
Thank You,