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Question about phase noise simulation result (Read 37367 times)
Frank Wiedmann
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Re: Question about phase noise simulation result
Reply #30 - Nov 25th, 2015, 12:53am
 
In general, there is no direct correlation between time domain (strobed, jitter) and averaged ("sources") pnoise results (see http://support.cadence.com/wps/mypoc/cos?uri=deeplinkmin:ViewSolution;DocumentTy...).
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deba
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Re: Question about phase noise simulation result
Reply #31 - Feb 21st, 2018, 3:54am
 
Hi,

It is a very useful thread.

I have few questions, I hope someone can answer.

If someone is designing a clock buffer circuit. The AM noise can be removed by passing the clock output through an ideal VCVS with gain of 1, centred around Vdd/2. Thus, there is only PM noise present in the circuit. Here the sources (time average) method can be used to calculate the phase noise.

But when I use PM-jitter for this circuit, the results are almost 2x compared to sources. Can some one please help in this? Is the method of using VCVS with voltage limit correct?

Thanks
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deba
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Re: Question about phase noise simulation result
Reply #32 - Feb 21st, 2018, 10:54pm
 
A follow up question.

Passing the clock output through an ideal VCVS of gain=1 and voltage limits of +/-100 mV around the threshold(mid-value) suppresses the AM noise? Is the above statement correct?
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