Dear all:

The switched capacitor integrator is as following. how to test the linearity of the integrator? I am consid [img][/img]ering to do it in following way.

1) Input is a pure sin wave, the do pss+pac, then calculate the iip3

2) input is a pure sin wave, the output is a stair-case sin wave, then sample the output and do DFT then watch the HD3.

Which way is better? Anyone watch this post must leave you idea. LoL!!

Thank you for your attention!!!

If you are asking for a choice between the two methods, then I would go with method (2) and do a DFT, simply because the dynamic range you can cover with a DFT is much larger. I assume that you will take care to perform coherent sampling so that you don't need to run an excessively long simulation.

On the other hand, the above integrator is really not seeing a dynamic sine input. It is only the sample-and-hold realized by the switches running in phi1 that are seeing this. If you can verify by other means (there are too many of those) that there is no appreciable limitation there, then your integrator is simply taking sampled inputs which are basically like DC. There are again many ways of characterizing the linearity of such an integrator. But then again, the best method depends on the kind of circuit this integrator is sitting inside. I suppose that this is only part of a larger loop.

Perhaps you are better off with method (2) after all...

Regards,
Vivek