there are several different ways of modelling a PLL in simulink - can you post a drawing of what you got?

I have attached the reference design. I'm wondering if lock detector i want to include into the dual-loop CDR, what is the compenent inside the block of the lock detector in simulink?

The concept of the lock detector is that at start up, the coarse loop will provide fast locking to the system frequency with the help of reference clock, after the VCO reach proximity of the system frequency, lock detector toggles the "lock" signal indicating that it is time for the fine loop to take over the control of phase locking.

Have anyone have ideas about how to model the lock detector together with the phase/frequency detector (PFD) together in matlab??

Thanks and appreciate alot.

HI loose-electron,

Yes, I come from Malaysia. Thanks for your reply. I manage to simulate the phase-frequency detector (PFD) alone to get the desired output.

However, i still not get it how you describe the lock detector in simulink? How i should design in simulink in order to differentiate the fine loop and coarse loop?

Thanks and aprreciate alot.

Hi loose-electron,

Do you have any simulink diagram regarding what you have suggesting your work?

thanks alot.
:)

Hi all,

I am sorry to post here 2 years afterwards, but I have a similar problem, and I didn't want to create a new thread on the same subject.

I am doing a macro-model of a PLL in Simulink and  I cannot put the PFD to work. I am using the usual block diagram: 2 DFF's, 1 AND gate, input and output ports. However this is not that easy. I have googled and I have found nothing. Can anybody help me ? I am stuck !!!

The goal of this is to have a functional PLL, and then add noise to each one of the blocks.

Cheers,
Pedro