I have attached the reference design. I'm wondering if lock detector i want to include into the dual-loop CDR, what is the compenent inside the block of the lock detector in simulink?
The concept of the lock detector is that at start up, the coarse loop will provide fast locking to the system frequency with the help of reference clock, after the VCO reach proximity of the system frequency, lock detector toggles the "lock" signal indicating that it is time for the fine loop to take over the control of phase locking.
Have anyone have ideas about how to model the lock detector together with the phase/frequency detector (PFD) together in matlab??
Thanks and appreciate alot.