ahhfyz
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Posts: 5
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Hi, everyone! I have a system including verilog (modules and sub-modules) and schematic. It can be simulated in SpectreVerilog, but failed in UltrasimVerilog: "Error found by UltraSim. ERROR (USIM-18610): The UltraSim simulator failed to parse the netlist. Correct the above errors and run the simulation again."
What should I do next? Thank you!
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