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loose-electron Senior Fellow Offline Best Design Tool = Capable Designers Posts: 1638 San Diego California	Re: high gain (>100 dB) and low power op-amp topology ? Reply #15 - Mar 07^th, 2012, 4:59am A much more fundamental question: Why so much gain? I am trying to think of any case where I have ever needed more than 80dB of gain.
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gsensor Community Member Offline Posts: 33	Re: high gain (>100 dB) and low power op-amp topology ? Reply #16 - Mar 8^th, 2012, 9:04am Hi loose-electron, I need to have a high gain to keep the value applied to vin+ equal as much as possible to vin-, as this could affect my sensor's measures. I also have noticed from published work that most of high gain op-amps are used in ADC or DAC to have a high precision.
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loose-electron

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Re: high gain (>100 dB) and low power op-amp topology ?
Reply #17 - Mar 8^th, 2012, 9:34am

differential pair input mismatch will become an issue long
before the systematic error associated with
a "non infinite gain" op-amp.

Generally, the approach taken is to find a way
to zero out offsets and other systematic errors.

That huge gain is probably not needed, or
becomes unimportant due to other sources of error.

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gsensor

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Re: high gain (>100 dB) and low power op-amp topology ?
Reply #18 - Mar 8^th, 2012, 12:31pm

Ok, thanks Loose-Electron.
Is there a way to lower the differential pair input mismatch from the beginning of the design (schematic), or only layout techniques can have an effect ?

I have follow RobG and Vladislav D advices in order to reduce the noise and the offset of my folded cascode opamp, essentially:

- High length, low gm and saturation operation �for current mirrors.
- High gm, high length and sub-threshold for input differential pair.

I have a high gain (87 dB) but also a very high offset: 272 mV (Measured by connecting the non-inverting input to GND and the inverting input in feedback configuration to Vout, Vout = Voffset).

I have noticed that keeping the cascode transistors in subthreshold contributed to the high offset considerably, so I kept them in saturation, giving offset = 272 mV, instead of 364 mV. Lowering the wide of input differential pair had also a positive effect on lowering the offset.

I tried to lower gm of mirror NMOS and PMOS as much as possible to keep a high gain (at least 80 dB) and maintain them in saturation. I have no clue how to lower this offset more. Is there something I'm doing wrong that I can't see ??

(schematic, gain/phase, and output simulations are attached)

Thanks,
your help is very appreciated.

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Folded_cascode_offset_prob.tar

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RobG

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Re: high gain (>100 dB) and low power op-amp topology ?
Reply #19 - Mar 8^th, 2012, 1:36pm

gsensor wrote on Mar 8^th, 2012, 12:31pm:

- High gm, high length and sub-threshold for input differential pair.

I think you mean "high width" for the diff pair.

You have something biased or sized incorrectly if you are seeing 272 mV of offset. With 87 dB open loop gain your simulated offset should be less than 100 uV unless you are running Monte Carlo or another mismatch analysis. Check the operating point of the devices.

I don't have time to untar your file. If you post a png or other graphic file we could all take a look at it.

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gsensor Community Member Offline Posts: 33	Re: high gain (>100 dB) and low power op-amp topology ? Reply #20 - Mar 8^th, 2012, 1:48pm yes, sorry high width.. ok Thanks, here's the schematic
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gsensor Community Member Offline Posts: 33	Re: high gain (>100 dB) and low power op-amp topology ? Reply #21 - Mar 8^th, 2012, 1:49pm output swing :
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RobG Community Fellow Offline Posts: 569 Bozeman, MT	Re: high gain (>100 dB) and low power op-amp topology ? Reply #22 - Mar 8^th, 2012, 2:36pm That operating point shows zero offset and the other plot looks normal. I'm not sure why you had more offset in the unity gain configuration. edit... I now see the input is connected together so of course the offset is zero.
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gsensor

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Re: high gain (>100 dB) and low power op-amp topology ?
Reply #23 - Mar 8^th, 2012, 7:37pm

yes, sorry, I should have told you that the configuration in the folded cascode schematic I posted was to test the open loop gain.

Indeed, I used a unity gain configuration to test the offset (right configuration on following image).

To the the output swing, I varied vin+ from -200 mV to 200 mV, and plotted the output voltage (vout) vs vin+ by using the left configuration on the following image.

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config_folded_cascode.png

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RobG Community Fellow Offline Posts: 569 Bozeman, MT	Re: high gain (>100 dB) and low power op-amp topology ? Reply #24 - Mar 8^th, 2012, 8:22pm Put the Vin+ input at midrail, not at 0 volts. The output can't pull itself all the way down to the bottom rail.
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loose-electron

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Re: high gain (>100 dB) and low power op-amp topology ?
Reply #25 - Mar 9^th, 2012, 7:24am

RobG wrote on Mar 8^th, 2012, 8:22pm:

Put the Vin+ input at midrail, not at 0 volts. The output can't pull itself all the way down to the bottom rail.

Agreed.

In addition

-- you need to estimate your offsets with real expected mismatches of your devices.
-- you need to size your transistors to get best matching available
-- you need to common centroid you matched sets of transistors

With all that you need to then determine
what your offsets will be with those things in place.

If you need better offset performance then you need to incorporate additional methods

-- static offset calibration methods
-- chopper methods to cancel offsets

Both would work

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gsensor

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Re: high gain (>100 dB) and low power op-amp topology ?
Reply #26 - Mar 9^th, 2012, 10:12am

For the offset measurement, I have put Vin+= 0V following the definition of what's an offset voltage: "if differential input voltage of ideal op-amp is zero, the output voltage is also zero. In real op-amp, there is an offset voltage..."

I'm not sure to understand what's the relevance of using vin+= 1.25 V instead..ain't my output suppose to be able to go all the way down to the bottom rail ?

Anyway, if I use vin+=1.25V, I have vout = 1.258535 V, so I guess my offset is 8.535 mV (without using a mismatch process analysis) �? :

Also, according to my output swing simulation, the output swing is 0.505 V to 2.21 V ? Why doesn't my transfer curve hit 0V at the bottom ?

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offset_vin1_25V.png

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RobG

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Re: high gain (>100 dB) and low power op-amp topology ?
Reply #27 - Mar 9^th, 2012, 6:24pm

gsensor wrote on Mar 9^th, 2012, 10:12am:

Also, according to my output swing simulation, the output swing is 0.505 V to 2.21 V ? Why doesn't �my transfer curve hit 0V at the bottom ?

Because T0 and T10 go linear, thus the amount of current they sink for the same gate voltage decreases. As they become more linear eventually they won't be able to overcome the PMOS current sources and the output will pull down no further.

You need to keep the output devices out of the linear region if you want good performance (i.e. high open loop gain).

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loose-electron Senior Fellow Offline Best Design Tool = Capable Designers Posts: 1638 San Diego California	Re: high gain (>100 dB) and low power op-amp topology ? Reply #28 - Mar 10^th, 2012, 12:48pm as a general rule you do not want o operat the device near ground, or near the power supply. You can design what is called a "rail to rail" (Power to ground) operational device, but that will require extra circuitry. I do agree with what RobG has said,.
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gsensor

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Re: high gain (>100 dB) and low power op-amp topology ?
Reply #29 - Mar 12^th, 2012, 9:45am

Ok, thanks a lot for your explanations and advices guys ! It helps a lot !

As RobG suggested me earlier, I will use a simple second-stage with Ahuja compensation to achieve the near rail-to-rail output swing I'm seeking.

RobG wrote on Mar 6^th, 2012, 7:08am:

I'm afraid the folded cascode topology might not give you the "near rail-to-rail" performance you require. If that is the case I would do a simple two stage amplifier with Ahuja-type compensation. Standard Miller compensation could also be used.
rg

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