Designer’s Guide Community

‹ Previous topic | Next topic ›

Pages: 1

asking about the implicit equation when using verilog-A (Read 90 times)

dabier

New Member

Offline

Posts: 2

asking about the implicit equation when using verilog-A
Feb 20^th, 2012, 3:40pm

I was doing a behavior modeling of electronics devices. and in the model i need to declare a real type variable. and this variable is a function of time and can be defined from a differential equation implicitly, so can i just put the equation in the model and will the simulator automatically handle this? i just know that only a contribution can handle this implicit equation, how about a variable? � thanks!!

IP Logged

Geoffrey_Coram Senior Fellow Offline Posts: 1999 Massachusetts, USA	Re: asking about the implicit equation when using verilog-A Reply #1 - Feb 21^st, 2012, 6:13am I'm pretty sure you'll need to set up a contribution to handle this; this will force you to select a discipline for the variable, which then sets the tolerances (absolute and relative) so that the solver knows how accurately it needs to resolve the value.
Back to top	If at first you do succeed, STOP, raise your standards, and stop wasting your time. IP Logged

dabier New Member Offline Posts: 2	Re: asking about the implicit equation when using verilog-A Reply #2 - Feb 21^st, 2012, 9:04am Thank you very much. i know what to do now!!
Back to top	IP Logged

boe Community Fellow Offline Posts: 615	Re: asking about the implicit equation when using verilog-A Reply #3 - Feb 23^rd, 2012, 3:36am dabier, you might want to try an indirect branch assignment: Code: V(out) : V(in) == 0 ; //find V(out) such that V(in) is zero - B O E
Back to top	IP Logged

Pages: 1

‹ Previous topic | Next topic ›