hello all,
i am reading a patent on charge pump for low spur PLL, find the attached fig.  but the basic problem is during M1,M2 turn on opamp has -ve feedback but how about feedback polarity when M5,M6 on.

Here i assume tail current source is realized by nmos whose gate is driven by opamp.

Thanks,
raj.

hello,
think about dc always, then ac.

Thanks,
Raj.

Hi raj.

I don't know what's the purpose of that charge pump scheme. But I think One node, like Vx, probably is set to a common mode voltage. So you remove one loop.


Yawei

hello anil,
whats the difference between my first post and your post?