I am interested on creating with Verilog-A a variable phase shift model for a sinusoidal input signal and I have tryed a lot of methods. I did use $absdelay, but it needs a constant delay time in order to use it. I did try also the transition operator, but it also could not provide variable phase shift. I did try to use both of the above into if or for loops, but Spectre says that these operators are not allowed to be used into a  conditionally executed statement.

Is there anyone who has any idea how I could implement a linear variable phase shift model?

The point is that when absdelay is used into an analog statement, its delay value is not allowed to change during simulation time (any changes in fact are ignored by simulator). I am aware of the maxdelay functionality, but unfortunatelly it can not operate in the way that I would like. I think that transition operator would work, since there's no problem with it changing its delay value inside an analog statement and during simulation time, but I can not figure out the way that I can create a linear change of the delay value inside the transition operator.