Hello Everyone,

I have a fundamental question regards to using the Phase Noise to estimate jitter for Sigma Delta. I can estimate the maximum sampling jitter for ADC as below:

For a Discrete Oversampling ADC, the maximum jitter can be computed as follows by the known expression:

J=(10-SNR/20)÷(2πfB).(√2.M),

where M=OSR, fB=Bandwidth of the ADC.

Usign the above expression for an OSR-133, BW=16kHz SNR=96dB

The maximum jitter allowed in sampling is: 2.56nSec (RMS)

For sampling the ADC, I am designing a ring oscillator generating 4.0MHz used as a sampling clock. I plotted the phase noise of the oscillator. My challenge now is for intgeration of phase noise what offset frequency lower limit should I use to compute jitter for my ring oscillator. Since I cannot violate the 2.56nsec.

The phase noise of my ring oscillator is as below


      offset freq         L(f)
1.    100Hz              -29.85dBc
2.    1kHz                -59.87dBc
3.    100kHz            -118.3kHz
4.    2.0MHz            -148.9MHz

so when integrating the above phase noise should I integrate from 100Hz to 8.0MHz or from 1kHz to 8.0MHz ?

Depending what BW I use for integration I get different jitter number. But I need to make sure I am not violating my 2.56nsec.

Todate, I have not found any literature that explains what lower integration limit for offset freqquency be used for oscillator based on ADC requirement.

Regards

ic_engr.

Frank,

Sorry, but when I went to the link it is talking about the noise intergration based on observation period.

My question is the lower integration limit in OFFSET frequency of oscillator phase noise plot.Any ideas ?

ic_engr