Hello everyone,
I am designing a divided-by-2 with SCL latch by 40nm low power technology. The supply voltage of the circuitry is limited to 1.1V, and the threshold voltage of transistor is about 0.6V.  As shown in simulation result in figure 2, there is a significant spike in the latch output waveform.
   In my opinion, the NMOS as tail current source is biased at triode region so that the ripple at node Y is large.  The ripple causes incomplete switch of the clock-driven differential pair. As a result, the input differential pair still amplifier input signal even when the clock is supposed to shut them down.
My questions are,
1. Is my analysis right?

2.  The circuity topology is three NMOS in stack. It is difficult to bias this circuit with the limited supply voltage and large threshold voltage. Can I abandon the tail current source to get an easier bias? It there any suitable topology?

3. Can my circuit be further optimized? It seems useless to adjust parameters in the circuit.  

Thanks in advanced,
Yutao

Yutao Liu wrote on Jun 15^th, 2012, 7:11am:


Try using a resistor instead of the current source.

loose-electron wrote on Jun 15^th, 2012, 9:52am:


The spike does exist with resistor, and the amplitude is the same as that with current source. But the swing(Vmax-Vmin) becomes larger.

I checked the circuit again and found that there is about 160uA gate leakage current in the clock-driven differential pair. I think this leakage also causes the spike, doesn't it?

Thanks,
Yutao Liu

Lex wrote on Jul 4^th, 2012, 12:38am:


The threshold is 0.6V when the length of FET is 40nm. And the threshold voltage decreases when length increases. In the schematic attached, the length of current source is above 40nm. So its bias voltage is lower than 0.6V.

Best,
Yutao