aaron_do
|
Hi Larry_80,
your circuit is quite confusing. Where are the inputs? I'm guessing the outputs are V1 and V2, right? But then why did you label the top resistors as ZL (load impedance)? So if I'm wrong and V1, V2 are the inputs, then why are you using PMOS? Also, from your schematic, it looks like RB and R are in parallel which means they can be replaced by a single resistor right?
Anyway, assuming V1 and V2 are the outputs, you can do a half-circuit analysis to see that your circuit does indeed reduce the DC input imepdance. However, I'm not sure if this is true for high frequencies since it depends on the loop gain 1+gmB(R||RB) which has an pole due to the output node. It also adds input capacitance to the circuit. If you want to be sure, you could do an ideal schematic using VCCS components with resistors and a couple of capacitors to double-check.
Another thing is that the main transistor has a positive feedback loop with the output, so if the loop gain is too high, the circuit may be unstable.
regards, Aaron
EDIT:
OK I had another look at your circuit, and it seems I'm wrong and the output is ZL. So now it looks a lot like a source follower except the input impedance without ZL is negative. So you're trying to develop a very large voltage at the input and then buffer it to the output? Actually my earlier analysis was still right, except I had it backwards, so it looks like your DC output impedance drops, but at high frequencies it is limited by the loop gain.
|