Hello Folks,
Please i am in dire need of opinions/helps or suggestions. Please find attached is a schematic of the circuit in question. transistor MB and resistor RB serve as feedback to the main stage. My questions are these:
1.) Does the feedback effectively boost the gm of M1 by the gain of the feedback stage (gmMB*RB)?
2.) Also what is Rout?
3.) This looks like the circuit is inherently unstable?

Please i could use any feedback as this as taken such a long time for me to figure out and i need opinions from the circuit gurus.

Thanks a lot!!

The gain of the amplifier will lower Rout, just like an opamp lowers the Rout of the 2nd stage (which also could be a source follower) I don't see any reason why it would be inherently unstable but you can add cap to Rb to compensate the loop.

You should define your inputs and outputs... what are you trying to do?

Thanks guys....I actually was trying to do exactly that....Lower Rout. But unfortunately, my circuit is osciillating....i have a cap load which i need to drive at the Rout node (sorry i didn't label it). I added the feedback for "BW extension" which made my circuit run at the frequency i wanted, but made my circuit unstable..pretty much have an oscillator . Any suggestions how to solve this?
Thanks guys for the response....appreciated... also the voltage i'm interested is at the Node across Resistor R.

put some compensation in the loop... a cap across drain/source of Mb.

Hi Larry_80,


your circuit is quite confusing. Where are the inputs? I'm guessing the outputs are V1 and V2, right? But then why did you label the top resistors as ZL (load impedance)? So if I'm wrong and V1, V2 are the inputs, then why are you using PMOS? Also, from your schematic, it looks like RB and R are in parallel which means they can be replaced by a single resistor right?

Anyway, assuming V1 and V2 are the outputs, you can do a half-circuit analysis to see that your circuit does indeed reduce the DC input imepdance. However, I'm not sure if this is true for high frequencies since it depends on the loop gain 1+g_mB(R||R_B) which has an pole due to the output node. It also adds input capacitance to the circuit. If you want to be sure, you could do an ideal schematic using VCCS components with resistors and a couple of capacitors to double-check.

Another thing is that the main transistor has a positive feedback loop with the output, so if the loop gain is too high, the circuit may be unstable.


regards,
Aaron


EDIT:

OK I had another look at your circuit, and it seems I'm wrong and the output is ZL. So now it looks a lot like a source follower except the input impedance without ZL is negative. So you're trying to develop a very large voltage at the input and then buffer it to the output? Actually my earlier analysis was still right, except I had it backwards, so it looks like your DC output impedance drops, but at high frequencies it is limited by the loop gain.

Hi guys,
I am trying to do STB analysis in cadence. I am pretty confused on how to break this loop since i have 2 feedback paths. One for cross-coupled and the other for gm boosting. I am more inclined to breaking it at the V1 or V2 point. Any advice will be appreciated.

Hi Aaron_do, yeah you are right it looks more like a common gate. I cannot replace with NMOS input pair because the long wire (with big cap) i am trying to drive is pre-charged to a level closer to VDD. (does this make sense?) (thats why i have a current source to model the precharger). Also could you confirm i have both positive feedback loops? i traced by hand and i keep getting positive feedback for the gm-boosting. How do i make this negative?? thanks for all your contribution and help!!!

i Aaron_do, any advantage of using an NMOS input pair? I will verify my idea using VCCS as you suggested. Thanks.