BackerShu
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Hi Mayank, very interesting question.
For digital implementation, as you said, it is understandable since the maximum phase update rate is somewhat a fixed value, which is depended on the proportional path gain. This paper has a pretty good explanation on it; just in case you haven't checked this paper yet. [1] R. C. Walker, “Designing Bang-Bang PLLs for Clock and Data Recovery in Serial Data Transmission Systems,” pp. 1–12.
For the analog CDR, I am not exactly sure. Here are my understandings to your three questions:
Q1: Yes, I think so, and the Phase Slew Rate is decided by the maximum speed charge pump can charge the capacitor in loop filter. In other words, it should related to Icp/sC.
Q2: Again, theoretically I think so, but this would be the minimum requirement of Phase Slew Rate to certain meet JTOL requirement. Some margin is necessary.
Q3: I am not sure what do you mean here. If you are still think about meeting the JTOL requirement, reduce the Slew Rate would be better since it will save some power.
Correct me if I am not right.
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