rampat
Junior Member
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Posts: 14
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Hi
I am trying to model bias current port using real number model as below
output real ibias[8:0]; In my testbench where I am instantiating this module I have defined real ibias[8:0] , but the issue is ncverilog is showing error when I pass this variable as .ibias(ibias[8:0])
error message : Part-select ot indexed part-select cannot be applied to memory [4.2.2(IEEE)].
Does this mean that i can not pass variable bus as port ?
Thanks
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