Hi,

I'm trying to model a simple counter in Verilog-A. The counter should simply count the number of positive clock edges of the input signal Clk.
I wrote the following code to model the behaviour:

@(cross(V(Clk)-Vtreshold, +1)) begin
   count = count + 1;
   $strobe(count)  //prints the value of the count variable

I simulated the counter in spectre for 5 clock cycles and hoped to
see the variable count printed out 5 times and increased to 5. However, it increased to about 100. It seems as the statements inside the @cross are evaluated several times when the crossing is detected.
I guess that I missunderstood the crossing function. Is there a way to
only detect the clock edge only once when the crossing is detected?  

Hi,

Thank you for your reply.
I've fixed it now.

Off course,

I think the problem was that I first copied the code from another
cell and forgot to change the module declaration. The module declaration was

module CellX(In, Out, Clk)

instead of

module Counter(In, Out, Clk),

while the name of the cell is still Counter.

As the code refers to another already existing module it will
cause strange behaviour. An advice is therefore to always check this
when finnished with the code.