Hi
I am getting unexpected output while simulating a SC integrator using a verilog-a model of opamp. I have tested a SC inverting gain stage and got desirable output
. For that circuit I have discharged the feedback capacitor in each clock pulse.
But for integrator circuit we need to keep the charge of feedback capacitor. When I am doing not discharging the feedback capacitor I am getting :-/unexpected output(like in KV range as I am not using opamp saturation condition).
I think this is probably due to no feedback at DC. Can anyone suggest anything about the circuit
.
Thank you