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PSS analysis failed using Verilog-A block
Jan 20^th, 2013, 1:14pm

Hi,

I was trying to run a PSS+Pnoise analysis for my VCO. But I needed a periodic signal (rectangular wave) as input to my VCO control (not a clock). But when I do PSS analysis it fails since the circuit was not autonomous, as it should be since I selected the "oscillator" option in PSS dialog box. As per suggestions on this forum, I tried creating a Verilog-A block which outputs a rectangular wave. I used the 1st code written by Ken Kundert here:
http://www.designers-guide.org/VerilogAMS/functional-blocks/osc/osc.va

It works fine in transient but now the PSS analysis says the variables 'n' and 'next' are hidden states and it is not supported by PSS analysis. Can anyone please suggest an alternative to this?

Thanks.

Regards,
Nikhil

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Ken Kundert Global Moderator Offline Posts: 2384 Silicon Valley	Re: PSS analysis failed using Verilog-A block Reply #1 - Jan 21^st, 2013, 9:41am If you drive the input of the VCO with a periodic signal, the output of the oscillator will not be periodic and so cannot be simulated with SpectreRF. What is it that you are trying to accomplish? -Ken
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aliasnikhil

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Re: PSS analysis failed using Verilog-A block
Reply #2 - Jan 21^st, 2013, 10:38am

The periodic input signal has nothing to do with the oscillation or the frequency. It is used to turn on and off some devices. Lets say we have 2 devices in parallel. So when one if off, the other will be turned on, thereby not affecting the oscillation. I need to do this in order to study noise effects. How do I do this?

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aliasnikhil

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Re: PSS analysis failed using Verilog-A block
Reply #3 - Jan 21^st, 2013, 10:07pm

To be more precise, I want to generate 2 voltage levels: Vdd and Vctrl as a rectangular waveform. It will in no way change the periodicity of the VCO. I could try to hard-code it in Verilog-A but I am not sure if Verilog-A allows use of statements like this:
begin
#(time delay1) statement1;
#(time delay2) statement2;
end

I am not sure if this Verilog code can be used with Verilog-A. And to be clear, I will need Verilog-A and not Verilog since I have to switch between Vdd(=1) and Vctrl (can be from 0 to 1, analog values).

Can anyone help?

Thanks!

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Ken Kundert Global Moderator Offline Posts: 2384 Silicon Valley	Re: PSS analysis failed using Verilog-A block Reply #4 - Jan 21^st, 2013, 10:12pm SpectreRF requires that the system be generating periodic waveforms, and all waveforms must be periodic with the same fundamental period. Thus, what you are trying to do will never work. If the drive signal does not affect the oscillator, perhaps you should simply remove the oscillator. -Ken
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aliasnikhil

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Re: PSS analysis failed using Verilog-A block
Reply #5 - Jan 21^st, 2013, 10:26pm

1) The drive signal will be periodic;
2) I can make it have the same fundamental period: there is no restriction on frequency of the drive signal;
3) I am trying to study effects of noise by this method and hence even though the drive signal does not affect the oscillation, it will affect the oscillator noise.

Any further thoughts/ideas?

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Ken Kundert Global Moderator Offline Posts: 2384 Silicon Valley	Re: PSS analysis failed using Verilog-A block Reply #6 - Jan 22^nd, 2013, 9:54am The drive signal will not be co-periodic with the oscillation. -Ken
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rfidea Senior Member Offline Posts: 159 Europe	Re: PSS analysis failed using Verilog-A block Reply #7 - Jan 22^nd, 2013, 12:58pm Can you vary your voltage level at each cycle of your oscillator? Then you can make the oscillator clock a device that toggles its output between those voltage levels. Is it possible to use transient noise?
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aliasnikhil

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Re: PSS analysis failed using Verilog-A block
Reply #8 - Jan 22^nd, 2013, 1:15pm

Hi,

I could try using another oscillator to provide signal to my main oscillator but it may inject noise through the gate of the main oscillator PMOS transistors (to which the drive input will be connected). So, I need a way to go about doing this.

Here is what I am trying to do:
My oscillator works as a free-running ring VCO. It has a control voltage (Vctrl) to change its frequency. I need to study the effect of noise in transistors connected to Vctrl. So if I make Vctrl=Vdd then I can turn them (PMOS) off. But this would stop the VCO. So, I am using 2 parallel devices (PMOS). When one of them is off, other will be on and vice versa and VCO will work fine. But the noise by switching them (PMOS) off for some time 'should' change and that's what I need to study.

1) I tried vpulse but it cannot work with PSS.
2) I tried Verilog-A but cannot find way to make it state-independent by using time delay statements like "#time_delay statement1; #time_delay statement2;" etc

Can you suggest any way to make No.2 work or any new method?

Thanks!

-Nikhil

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rfidea

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Re: PSS analysis failed using Verilog-A block
Reply #9 - Jan 23^rd, 2013, 9:36am

Transient noise is part of Spectre transient analysis. You just switch it on in the transient analysis. I have not used it myself but it should introduce noise in your transient analysis and then you can do an fft to the the noise level.

What are you trying to do? Are you trying the see how the noise varies during the time you change a input signal? Is there a specification on that? I have never seen such a specification. I think is is difficult to use PSS for that.

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aliasnikhil

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Re: PSS analysis failed using Verilog-A block
Reply #10 - Jan 23^rd, 2013, 10:48am

Hi,

Thanks! Doing an FFT seems a nice idea. I will try it and see if I can make it work. Thanks. I had the same idea earlier but does enabling "transient noise" do the same job as PNoise?

Here is one of the recent papers that did what I am trying: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5289642

I am not sure if you have time to go through this but if you do, then Figure 3. on Page.2 is what happens to noise when you turn ON-OFF a MOSFET. And Figure.5 on Page.4 is the circuit diagram of what I am almost trying to accomplish. Also, on Page.4 they mention "Phase Noise analysis have been done in spectreRF..." under "Simulation results". So it is do-able but I can't figure out how. But even they are using a clock to drive the "switching bias" part of the VCO. How come they didn't face problems like me? :o

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rfidea Senior Member Offline Posts: 159 Europe	Re: PSS analysis failed using Verilog-A block Reply #11 - Jan 24^th, 2013, 11:01am pnoise and transient noise should give the same results but they work totally different. I do not have access to the article you refer to so I do not understand what you trying to accomplish.
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kentam

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Re: PSS analysis failed using Verilog-A block
Reply #12 - Jan 24^th, 2013, 5:00pm

Hi,

I encounter the exact same problem as you do. I am designing a relaxation oscillator (current source, cap, and comparator). I did chopping for my comparator with chopping clock coming from an external ideal vpulse source. However PSS with "oscillator" option turned on didn't run successfully because the oscillator is an non-driven circuit. Therefore I got my oscillation frequency from transient and I set my chopping frequency to be 2 times of my oscillation frequency, and I turned off "oscillator" option in PSS. (just to try having PSS working for phase-noise simulation). It worked finally but the phase-noise below the 1/f corner didn't make sense.

I then did an experiment with my relaxation oscillator without chopper. I simulated the phase-noise with PSS "oscillator" turned on and turned off, and the phase-noise below the 1/f corner didn't agree with each other, while phase-noise above 1/f corner were the same. As a result I am not be able to get the phase-noise performance at low offset frequency...

Since later I would also like to proceed with measuring the oscillation frequency with sweeping temperature. In that case, the chopper frequency will no longer be always the multiple of the oscillation frequency, then PSS won't work anymore... I tried Ken's verilog-a VCO but it didn't work due to hidden state problem.

Ken, is it possible if you can take a look of the oscillator you written in verilog-a and see if it can be implemented in a way that it will be hidden-state free? Or do you have any other suggestions?

Any help would be appreciated! Thanks a lot!!

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Ken Kundert

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Re: PSS analysis failed using Verilog-A block
Reply #13 - Jan 24^th, 2013, 10:46pm

Transient noise would work in this case, but it is problematic because it would require very long simulation times to resolve the low frequencies in the flicker noise.

You cannot drive the oscillator with a fixed frequency oscillator. If the signal is large enough for the oscillator to lock to it, the phase noise will be suppressed exactly in the same way that phase noise is suppressed in a PLL. If the signal is not large enough for the oscillator to lock to it, then the resulting system will be non-periodic and SpectreRF will not converge.

I recommend that you connect a divider to the output of the oscillator and use the output of the divider to modulate the bias on the PMOS FET. Try to choose the smallest divide ratio you can. The larger the divide ratio, the longer the simulation. When providing the probe nodes for the PSS analysis, you need specify nodes at the output of the divider.

Unfortunately, this may all be for not. I believe the noise reduction technique you are trying to simulate counts on an effect that is not modeled in any MOSFET model I am aware of.

-Ken

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