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IP3 simulation: 3rd order plateau
Jan 24^th, 2013, 1:07pm

Hi All,
I'm simulating IP3 of an amplifier using PSS and PAC, and I've noticed something strange about the 3rd harmonic (see attached image). At moderate power levels, the 3rd follows a 3dB/dB slope (as expected). At higher power levels, the slope of the 3rd increases (as expected). At low power levels, the 3rd deviates from a 3dB/dB slope and, as the input power is decreased, the power in the 3rd stops decreasing, which seems like it might be non-physical. The attached image (upper left corner) shows the IP3 behavior that I'm talking about. This behavior is also visible in PSS-only simulations (see bottom plot in which I have plotted the frequency as a continuous line instead of sticks). My setup is rather involved, but I can provide specifics as needed. Has anyone seen this problem before?
Thanks in advance!
Dave

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IP3plateau.png

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rfidea Senior Member Offline Posts: 159 Europe	Re: IP3 simulation: 3rd order plateau Reply #1 - Jan 24^th, 2013, 3:06pm It could be an accuracy issue. Maybe your HD3 is down in the numerical noise floor. Try to increase the accuracy in the simulation.
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Dave Jackson

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Re: IP3 simulation: 3rd order plateau
Reply #2 - Jan 25^th, 2013, 9:55am

Hi rfidea,
Thanks for your reply. I also suspected that it was an accuracy issue, so I have tried tightening accuracy settings down as listed below. Also, I'm being guided by this post from Tawna Wilsey: http://www.designers-guide.org/Forum/YaBB.pl?num=1173722684

Here are some of the settings that I've tried:
reltol: started with 1e-5, went to 1e-7
method: started with gear2only, tried trap and traponly
gmin: 1e-12 and 1e-13
tolerance: tried conservative and moderate
relref: normally set to default, tried pointlocal and alllocal
tstab: normally zero, tried 50ns (period of fundamental is 33.33ns)
iabstol: 1e-11 or 1e-12
lte: default (3.5)

When faced with convergence difficulties, I tried cmin=100aF

I don't see any sensitivity of the described plateau to any of the above settings. Of course, tightening the tolerances does reduce the noise floor (I see the even harmonics go down significantly) but the odd harmonics continue to show the plateau.

Additional thoughts?
Thanks again,
Dave

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RFICDUDE

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Re: IP3 simulation: 3rd order plateau
Reply #3 - Jan 25^th, 2013, 4:10pm

Hi Dave,

This type of behavior may be a limitation of the CMOS model. One way to test this is to have a test circuit on the same schematic that is an ideal 3rd order nonlinearity

a₃*x(t)³

and run a copy of the input signal through the ideal model. If the ideal model holds a 3:1 slope but the amplifier doesn't then the issue is likely in the model.

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Dave Jackson

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Re: IP3 simulation: 3rd order plateau
Reply #4 - Jan 25^th, 2013, 5:33pm

Hi RFICDUDE,
Your response is really interesting -- I have suspected the CMOS models, and I have tried JU, JURG, and JULEAK for certain key devices, with no differences seen. �Here's what I mean by "key devices": My amplifier has several gain settings, with the gain set by a FET switch in the feedback path (see image below). �I consider the FET switch to be a key part of the problem based on the following tests that I have run:
1) Ideal amp, ideal feedback (i.e. no FET switches) -> 'normal' IP3
2) Ideal amp, real feedback (i.e. with FET switches) -> 'normal' IP3
3) Real amp, ideal feedback (no FET switches) -> 'normal' IP3
4) Real amp, real feedback -> plateau in IP3

My conclusion was that somehow the FET switches are interacting with my actual amp (in terms of the models) to create the plateau, but I can't figure out what might be happening. �Of course, I also tried complementary switches, and I tried changing the bulk and gate bias. �I even tried adding non-linearity to my ideal amp, but couldn't reproduce the problem.

Do you have further suggestions regarding the CMOS models? �The real amp is a bi-cmos design (mostly bipolar with PMOS mirrors).

Thanks!
Dave

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IdealAmpSetup.png

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RFICDUDE

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Re: IP3 simulation: 3rd order plateau
Reply #5 - Jan 26^th, 2013, 2:46pm

The feedback switches could very well be the issue. It is known that many of the MOSFET models are not symmetric about Vds=0. The MOSFETs are physically symmetric about Vds=0, but the nonlinear models are not.

If you have any MOSFET devices in the signal path where the nominal value of Vds=0 (floating switches) then the models could be a problem for accurately predicting linearity performance.

To my knowledge, the MOSFET models that DO NOT have this problem are the EKV, PSP and the BSIM6 models. All BSIM models through BSIM4 do have the problem.

If you don't have access to EKV, PSP or BSIM6 models then some possible choices are

1. simulate linearity without using MOSFET models for the devices where Vds=0

2. intentionally add a (simulation only) bias to the Vds=0 devices to force Vds to be something other than zero

I don't think the asymmetry problem is an issue for OFF devices, so you may only need to worry about devices/switches that are on. You could add some bias current directly across the drain source to force a voltage of Ids*Rds. Of course you must be sure that the current is only circulating through the desired devices; otherwise, the added current may change the operating point of other devices in the circuit (not good).

I suggest first try simulating with the Vds=0 devices removed from the signal path to verify if this is the problem or not.

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Frank Wiedmann Community Fellow Offline Posts: 678 Munich, Germany	Re: IP3 simulation: 3rd order plateau Reply #6 - Jan 28^th, 2013, 1:14am See also http://www.designers-guide.org/Forum/YaBB.pl?num=1207474039.
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Dave Jackson

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Re: IP3 simulation: 3rd order plateau
Reply #7 - Jan 28^th, 2013, 10:31am

Hi RFICDUDE and Frank Wiedmann,
Thank you so much for your answers! �You've made my day by providing such clear explanations that so obviously explain my problem. �I'm going to look into the other models that we have available, and I'm also going to try forcing the devices to stay away from VDS=0. �I had already proven that removing the on-state devices (and replacing them with shorts) eliminates the problem, but I really didn't know why until your posts. �I had also proven that the off-state devices do not contribute to the problem, just as RFICDUDE asserted. �Thanks again for your excellent replies.
Dave

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RFICDUDE Community Fellow Offline Posts: 323	Re: IP3 simulation: 3rd order plateau Reply #8 - Jan 28^th, 2013, 7:35pm I am glad that we (this site) could be of assistance. I was not aware of the other models mentioned in the link Frank referenced, so I learned something too.
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weber8722

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Re: IP3 simulation: 3rd order plateau
Reply #9 - Feb 19^th, 2013, 7:31am

Hi,

my favorite on IP3 simulation is using not pss + pac, but using pss+pac with rapid-IP3 option. You can define multiple power levels to check if slope is fine. The accuracy level of rapid-ip3 should be better, but of course the vds=0 modeling problem will remain (bullshit in -> bullshit out)! On the other hand: in any good mixer design the IP3 should be degraded by the mixing transistors...

Bye Stephan

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