I have designed a linear regulator with a two-stage amplifier with an nmos  driver. I used miller capacitor and a nulling resistor for compensation at the second stage. I also checked the frequency response and the phase margin are quite good (90 deg and even more) across different load current (max ~1mA). However, when I did a transient sim at a particular load current (200uA), I saw oscillation at the output. It puzzles me becoz the frequency response satisfies the stability criteria at that load current.

Could the miller compensation make the second stage a potential oscillation source? Should I separate it from the first stage and output to check its stability? Any idea to overcome?  Thanks

For a NMOS driver i.e. power device, the O/P impedance is maximum at minimum load current condition. The dominant pole is located at the first stage of amplifier/the non-dominant poles are located at amplifier output and load. You want to test your stability in the zero-load-current condition to simulate the worst-case. This is unlike the case for a PMOS power device, where peak current is the least stable bound.

-Aman

Raj,

I guess the answer is a bit tricky and depends on high-frequency PSRR i.e. compensation design. Generally speaking in PMOS driver designs dominant pole is located at the output, which is not the case in NMOS driver type designs. So, for a NMOS driver LDO the dominant pole at error amplifier remains somewhat fixed and the parasitic/secondary pole O/P at low currents move close-in. Thus, if you are coming from a PMOS LDO design, worst-case scenarios might get reversed.

-Aman