Hi All,

I have built a simple behavioral model for a PLL, basically following what is described in the paper available in the site.

I am having an understanding issue with respect to phase PSD Vs. phase noise.

What is their relationship? Is it just that phase noise is phase PSD divided by carrier power?

Considering the different contributors, for

- main divider
- crystal
- VCO

I can simulate phase noise directly. So I have a relative measure, and through the phase-domain transfer function from the respective points to VCO output, I think I can be sure to calculate/simulate the right effect.

What about PFD/Charge Pump and Loop Filter noise? They are absolute current and voltage PSDs.
What I now have is PFD/CP's current PSD as input to the LF, and the resulting output voltage PSD as a result of thermal LF noise plus CP current noise.
Is it correct to inject this voltage noise at VCO's tuning port, and treat what comes out in terms of VCO phase PSD, as phase noise?
In other words, can I consider the open loop transfer function from v_tune port of the VCO to phase noise as being equal to

(2Pi*Kv/(j*w))**2

Thanks for reading and for any suggestion/insight into this!!

Michele