Hi all,


I am trying to port the design of a ring oscillator over from 65nm technology to 40nm technology, and I've run into a road block. I ran a noise simulation on a diode connected MOSFET (same size in both processes) with a fixed DC current flowing through both, and checked the noise voltage at the drain node. I noticed that for the 40 nm technology, the noise performance is about 3-4 times worse across the spectrum. Both technologies are from the same fab house, and I have tried several different transistors (lvt, nominal vt, dnw, IO) and all show a huge degradation in noise performance. I have also checked the gm of the devices and they are very close (within around 1%).

Does anybody know if this is a real effect?


thanks,
Aaron

Hi raja.cedt,


thanks for the reply. Would I expect to see such a huge difference for a transistor alone (3-4x degradation)?


thanks,
Aaron

Hi Aaron Do,

8/3 KT gm is for long channel technologies.
If you look at the noise modeling for thermal noise in BSIM3V3 or BSIM4 Manual, you will know that drain current noise is no longer valid with 8/3 factor.
But you can get this constant from simulation as,
gamma=f(VDSAT,L)

What you can do is, extract gamma for 65nm and 40nm technology. I think this will tell the real story for  the discrepancy.