Lynn Lou
Junior Member
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Posts: 18
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Hi all, I was doing a RF/Digital-Mixed simulation, in which I employed a counter to evaluate the divided RF signal. However, I found the counter gives a wrong value. At first, I thought the verilog code of the counter maybe has some faults. Eventually, when I lower the input signal frequency to 0.9GHz, the counter output the right value.
Does the spectreVerilog only support the clk of the digital module under, say, 1GHz?
Thanks.
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