Aaron,

  You don't mention how fast you want to run the ADC. Given that it is
a flash, the implication is that it needs to run fast. One issue is that
comparator gain is proportional to overdrive. As a result, the
comparator that needs to make the key decision is also the slowest
comparator and you can't sample until the comparator decides.
Another issues is that the input signal is not stable, that is, without
a S/H the input can slew while the comparators are trying to decide.
Due to delay, process variation, etc. more than one comparator
can be saying "I'm the one". The bottom line is that a flash ADC
without an S/H is almost always slower than a flash ADC with a S/H.

  We haven't even gotten to the issue practical issue of layout,
most designs are folded to improve the form factor. Folding
the ADC into four banks of 6 bit ADCs will cause clock skews
that will post comparator sampling unfeasible.

                                                                   Sheldon

Generally we do S/H followed by quantization since S/H is highly non-linear process. So, if Quantization is done first then output which is highly non-linear & on top of it, if you are doing S/H on top of it, then you will have your signal frequency spread throughtout ur fft plot. Although theoritically possible, it's not done generally in practical scenerios.