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A question about VCO phase noise simulation in time-domain PLL behavior model (Read 12004 times)
carl_chao
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A question about VCO phase noise simulation in time-domain PLL behavior model
Nov 13th, 2013, 7:54am
 
Hi,

I just wrote a time-domain PLL behavior model including VCO phase noise and non-idealities from other blocks. I have generated the time-domain open-loop VCO 1/f^3+1/f+white phase noise as shown below:


In the PLL time-domain behavior model, I inserted the above VCO open-loop phase noise at the output of the VCO according to this reasoning: At the current calculation time step, test if the phase of the VCO output is at or crossing 0 or N*2*pi (N is an integer). If yes, then insert this noise into the VCO output phase. After doing this (with all other non-idealities switched to ideal), I got the phase noise of the PLL as following:



As you can see from this figure, the high-frequency phase noise of the open-loop VCO directly showed up in the PLL output, while the low-frequency part was suppressed.

Now, my question is, whenever I put the VCO into ideal or changed VCO open-loop phase noise to white noise only, the phase noise curve of the PLL output would be very smooth (i.e., without any spurs as shown in the 2nd figure, but certainly with white noise, the noise floor increased). But whenever I added 1/f^3 and/or 1/f noise to the VCO, these spurs would show up. The frequency of the lowest spur is at the PLL input reference frequency, and all others are at its multiples. If these spurs are real, or just errors due to my modeling method?

If these spurs are real, I wonder if I can give the following explanation: after adding the 1/f^3 and/or 1/f noises, because of the near DC nature of these noises, at each input reference clock period, the charge pump mostly needs to put out a same-polarity pulse to compensate this DC bias, in an effort to align the frequency of the VCO with that of the reference input. This process is equivalent to having a charge-pump with mis-matched up-down currents, which we know will give rise to reference leakage to the output.
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« Last Edit: Nov 14th, 2013, 7:33am by carl_chao »  
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tm123
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Re: A question about VCO phase noise simulation in time-domain PLL behavior model
Reply #1 - Nov 14th, 2013, 6:55am
 
carl_chao,

If you can add the pictures I will try to help figure out what is going on here..
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carl_chao
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Re: A question about VCO phase noise simulation in time-domain PLL behavior model
Reply #2 - Nov 14th, 2013, 7:35am
 
tm123 wrote on Nov 14th, 2013, 6:55am:
carl_chao,

If you can add the pictures I will try to help figure out what is going on here..



Hi tm, Thanks for the reply!  It's strange, I can see the pics.  DOn't know how to attached multiple pics in one reply.  Here is the first pic: open-loop vco noise

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vco_001.jpg
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carl_chao
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Re: A question about VCO phase noise simulation in time-domain PLL behavior model
Reply #3 - Nov 14th, 2013, 7:36am
 
tm123 wrote on Nov 14th, 2013, 6:55am:
carl_chao,

If you can add the pictures I will try to help figure out what is going on here..


Here is the 2nd pic: the pll output noise
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pll.jpg
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tm123
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Re: A question about VCO phase noise simulation in time-domain PLL behavior model
Reply #4 - Nov 14th, 2013, 12:36pm
 
carl_chao,

The first thing that sticks out to me is that your VCO phase noise is extremely low. What is the center frequency of this VCO?  The spurs look pretty nasty but again the magnitude is extremely low for reference spurs.

Also, if this is a time domain Matlab model then you may have the ability to plot different signals such as the VCO output waveform, loop filter voltage etc.  It may help to check these out as well.

Tim
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carl_chao
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Re: A question about VCO phase noise simulation in time-domain PLL behavior model
Reply #5 - Nov 14th, 2013, 1:45pm
 
Hi Tim,

The center frequency of the VCO is 12,288MHz.  I'm just scaling the VCO noise to check its effect on the PLL output.  With this PLL output, I sampled a ~60kHz sinewave signal and got about 100dB SNDR (for ~200kHz bandwidth).  Here is the comparison of the input reference (at 32kHz) and the divider output:
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div.jpg
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carl_chao
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Re: A question about VCO phase noise simulation in time-domain PLL behavior model
Reply #6 - Nov 14th, 2013, 1:46pm
 
Here is the control voltage response:
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vctrl.jpg
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tm123
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Re: A question about VCO phase noise simulation in time-domain PLL behavior model
Reply #7 - Nov 15th, 2013, 7:53am
 
carl_chao,

OK, it looks like the loop is locking but there is clearly ripple on the control voltage.  You say that if you make the VCO noise white these spurs are not present, so there must be something going on with the 1/f noise response influencing the loop behavior like you described.  In real life I don't think this happens unless you have a huge amount of 1/f noise because the noise does not actually go to infinity at DC but if you are using an equation to model the 1/f noise that does go to infinity at DC that could be your problem.  Very large VCO gain could also cause issues like this.  Is it possible to define the noise as a vector with only discrete frequency points, for example only define the noise at 100Hz, 1KHz, 10KHz, etc.?

What is your ultimate goal in developing this time domain model?  If you are just trying to find the total phase noise of your PLL, you may be better off writing a phase domain model instead of time domain model.  There are several references on how to do this, including one written by Ken that I think you can access from this site.  If you are trying to model spur performance, in particular fractional spur performance, then I think it makes more sense to use a time domain model since you need to account for CP mismatch/nonlinearity and other nonlinear PLL components.

Hope this helps.

Tim
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carl_chao
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Re: A question about VCO phase noise simulation in time-domain PLL behavior model
Reply #8 - Nov 15th, 2013, 10:02am
 
Hi Tim,

Thank you very much for the analysis!

Perhaps it's due to my 1/f noise generator.  Here is the time-domain VCO phase noise (in radiants) the model generated: vcot.jpg



I generated the time domain 1/f noise according to the paper: 1/f^k noise generated by scaled Brownian motion" by Z. Gingl, Solid State Communications, Vol. 71, No. 9, 1989. The 1/f^3 noise is just an integration from it.

The original intention for me to write this model was to check the influence of long-term jitter on the performance of (especially) oversampled switched-cap ADCs.  But after doing some research, I found (at least to me) that the definition and the way of adding noises to VCOs in most of the currently published studies on PLL behavior models are not quite right Smiley.  Also, I have put most of the necessary non-idealities into the model, like: the reference clock jitter, PFD delay and minimum output pulse width (for avoiding dead zone), charge-pump up-down mismatch, current noise, leakage, current finite ramping, LPF resistor thermal noise, VCO phase noise, divider delay and noise, etc..

Best,

CZ
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vcot.jpg
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wandola
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Re: A question about VCO phase noise simulation in time-domain PLL behavior model
Reply #9 - Nov 15th, 2015, 5:24pm
 
im very interested to know to you obtain the PLL output phase noise.

I am working on an ADPLL model in time domain. I obtained time stamp of DVO output. It is an array of frequency numbers. I honestly don't know how to process the data and see the fft plot.

need some help on this.
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