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analog geek Junior Member Offline Posts: 15	Low drop out voltage regulator Nov 16^th, 2013, 4:53pm I am working on 90 nm LDOs. I am working on to convert 1.8 v to 0.8 volt range..any suggestions will be helpful. Thanks
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analog_rf Junior Member Offline Posts: 15 Universe	Re: Low drop out voltage regulator Reply #1 - Nov 26^th, 2013, 6:34am please let us know what you need specifically. Eg:what specifications you need to achieve ,what application is it going to be used(eg:pll vco etc). Noise requirements,PSRR.
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venkatesh juturu New Member Offline Posts: 6 vellore	Re: Low drop out voltage regulator Reply #2 - Nov 27^th, 2013, 9:10pm hi sir, i am designing VCO in cadence-virtuoso-ADE using gpdk180nm for the ckt shown as i got op waveform as shown and i changed corresponding w/l ratio and vdd i got another waveform my question how to stabilize the output waveform help in this regard thank in advance
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venkatesh juturu New Member Offline Posts: 6 vellore	Re: Low drop out voltage regulator Reply #3 - Nov 27^th, 2013, 9:11pm the output waveform
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venkatesh juturu New Member Offline Posts: 6 vellore	Re: Low drop out voltage regulator Reply #4 - Nov 27^th, 2013, 9:13pm the modified w/l output
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dave_dave

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Re: Low drop out voltage regulator
Reply #5 - Nov 27^th, 2013, 11:40pm

hi venkatesh,

what happens if you increase your simulation time? It looks like your system is not settling within your chosen simulation time.
You should also have a look at the amplitude of your signal: it's in the picovolt range, so it is not really a signal at all.

p.s. the topic does not really fit to LDOs Wink

greets
dave

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analog_rf

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Re: Low drop out voltage regulator
Reply #6 - Nov 29^th, 2013, 8:12pm

looks like with increased w/l your circuit is indeed oscillating.Please increase the simulation time and allow the output to settle to its final value which will be limited by the non-linearities of the circuit.what vco topology are you trying to design and what are your design requirements?eg:output freq,output phase noise@1Mhz etc.

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