Hi all,


for a pipelined ADC, people talk about the settling time requirements of the MDAC. For instance, it may be required to settle to within 10b accuracy.

For 40nm CMOS, I have noticed that the gate leakage of my OTA is not trivial, and this is making it difficult to really see what is the settling time of the OTA. i.e. If we cannot see the final value, how can we know the 10b accurate value. Anybody have any idea to get around this?

One thing which I think might be a good compromise (and maybe more meaningful in my opinion) is to use "sampled PAC" analysis from spectrerf. I can then look at the "10b accurate bandwidth" of my MDAC. Can anybody confirm whether this is a good design method?


thanks,
Aaron

A well-designed pipelined ADC essentially operates on DC samples, so the transient settling time is everything.  I would focus on transient analysis to find out what your MDAC is capable of.  Keep in mind that if you are calibrating for gain errors then linear settling errors will be calibrated.  Then you will be limited by settling nonlinearity due to slewing.

In fact, the RC of the front-end S/H will most likely set your high frequency bandwidth limit.  WHen the S/H starts significantly phase shifting you will get distortion.  Check the resistance of your input sampling switch and see how it varies.

In a previous question you ask about removing the input S/H.  Keep in mind that relying on redundancy to fix sampling skew only works well at low frequencies.  At higher frequencies it becomes increasingly difficult to match the amplifier and the sub-ADC path and you will quickly eat up all your correction range with aperture errors.  So be careful.

aaron_do wrote on Jan 5^th, 2014, 5:37pm:


That sounds about right.  As you can see the matching of the MDAC and subADC paths becomes pretty tight at high frequency.

You're also correct that a background calibration like you described would make this problem worse.  That's because these algorithms depend on using the correction range to inject their test signals.  I imagine it is somewhat involved to specify the comparator offset in this case.

If you have a front-end SHA then this matching issue goes away.  But you have to pay with a lot of power.

However, keep in mind that if you eliminate the SHA you will increase the required power in the comparators because you will need to keep the offset down.  Dynamic offset typically dominates the offset of a CMOS comparator in deep submicron technology.  It is very difficult to simulate accurately so you often over-design with a class-A preamp and dedicated sampling caps for the subADC.  It's a delicate tradeoff to be sure.

I'm not sure what you mean by "main source of high-frequency error".  What error specifically are you talking about?  Distortion in the sampling switch limits the SFDR at high frequency.  Incomplete MDAC settling limits the SNDR.  If you don't have a SHA my guess is mismatch between the MDAC and subADC would limit your sampling frequency.  

If you're going for high accuracy too, don't forget jitter in your sampling clock can also limit your sampling rate.  Pipelined ADCs are fun.

aaron_do wrote on Dec 1^st, 2013, 10:38pm:


Are you talking gate leakage from the input pair? I would think the error would be common mode. I didn't see any gate leakage effects in my 40 nm pipelined design.

By the way, if the output doesn't settle it doesn't matter if it is from slow response time or gate leakage - it is in error!